Displaying 2 results from an estimated 2 matches for "addiurxrximmx16".
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addiurxrximm16
2012 Aug 30
1
[LLVMdev] PHI
...B#1
%A0<def> = LwRxRyOffMemX16 %S0, <ga:@.str>[TF=2]; mem:LD4[<unknown>]
%V0<def> = LwRxRyOffMemX16 %S0, <ga:@printf>[TF=3]; mem:LD4[GOT]
%A1<def> = LwRxRyOffMemX16 %SP, 20; mem:LD4[%i]
%T9<def> = Move32R16 %V0
%A0<def,tied> = AddiuRxRxImmX16 %A0<tied>, <ga:@.str>[TF=6]
%GP<def> = Move32R16 %S0
JumpLinkReg16 %V0<kill>, <regmask>, %A0<imp-use,kill>,
%A1<imp-use,kill>, %GP<imp-use,kill>, %T9<imp-use,kill>, %SP<imp-def>,
%V0<imp-def,dead>
%V0<def> = Lw...
2013 Feb 08
2
[LLVMdev] pattern matching order
It seems that patterns are matched in the order that they appear in the
td file.
Is this something we can rely on?
def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
the immSExt8 will only match a 8 bit signed value.
I want it to try the first pattern and then the second, if it fails.
AddiuRxRxImm16 --- 16 bit instruction
AddiuRxRxXImm16 -- 32 bit instruction