Displaying 1 result from an estimated 1 matches for "addiurxrximm16".
2013 Feb 08
2
[LLVMdev] pattern matching order
It seems that patterns are matched in the order that they appear in the
td file.
Is this something we can rely on?
def: ArithLogicI16_pat<add, immSExt8, AddiuRxRxImm16>;
def: ArithLogicI16_pat<add, immSExt16, AddiuRxRxImmX16>;
the immSExt8 will only match a 8 bit signed value.
I want it to try the first pattern and then the second, if it fails.
AddiuRxRxImm16 --- 16 bit instruction
AddiuRxRxXImm16 -- 32 bit instruction