Displaying 4 results from an estimated 4 matches for "addgc".
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addc
2005 Jul 25
2
[LLVMdev] How to partition registers into different RegisterClass?
...rClass<packed, 128, [C0, C1]>;
def ADDgg : BinaryInst<0x51, (
ops GeneralPurposeRC :$dest,
ope GeneralPurposeRC :$src), "add $dest, $src">;
def ADDgi : BinaryInst<0x52, (
ops GeneralPurposeRC :$dest,
ope InputRC :$src), "add $dest, $src">;
def ADDgc : BinaryInst<0x52, (
ops GeneralPurposeRC :$dest,
ope ConstantRC :$src), "add $dest, $src">;
The problem is: SDOperand alwasy return the 'type' of the value (in
this case, 'packed', the first argument of RegisterClass<>), but not
the 'RegisterClass...
2005 Jul 23
0
[LLVMdev] How to partition registers into different RegisterClass?
On Sat, 23 Jul 2005, Tzu-Chien Chiu wrote:
> 2005/7/23, Chris Lattner <sabre at nondot.org>:
>> What does a 'read only' register mean? Is it a constant (e.g. returns
>> 1.0)? Otherwise, how can it be a useful value?
>
> Yes, it's a constant register.
>
> Because the instruction cannot contain an immediate value, a constant
> value may be stored in
2005 Jul 23
3
[LLVMdev] How to partition registers into different RegisterClass?
2005/7/23, Chris Lattner <sabre at nondot.org>:
>
> What does a 'read only' register mean? Is it a constant (e.g. returns
> 1.0)? Otherwise, how can it be a useful value?
Yes, it's a constant register.
Because the instruction cannot contain an immediate value, a constant
value may be stored in a constant register, and it's defined _before_
the program starts by
2005 Jul 26
0
[LLVMdev] How to partition registers into different RegisterClass?
...> def ADDgg : BinaryInst<0x51, (
> ops GeneralPurposeRC :$dest,
> ope GeneralPurposeRC :$src), "add $dest, $src">;
>
> def ADDgi : BinaryInst<0x52, (
> ops GeneralPurposeRC :$dest,
> ope InputRC :$src), "add $dest, $src">;
>
> def ADDgc : BinaryInst<0x52, (
> ops GeneralPurposeRC :$dest,
> ope ConstantRC :$src), "add $dest, $src">;
>
> The problem is: SDOperand alwasy return the 'type' of the value (in
> this case, 'packed', the first argument of RegisterClass<>), but not
&g...