Displaying 3 results from an estimated 3 matches for "add28".
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add2
2012 Jul 15
0
[LLVMdev] Issue with Machine Verifier and earlyclobber
...= fmul float %mul17, %call
%sub20 = fsub float %mul16, %mul19
%mul21 = fmul float %sub13, 4.000000e+00
%mul22 = fmul float %mul21, 0x3FF1F736C0000000
%mul24 = fmul float %mul22, %call
%call26 = tail call float @dcos(float %mul14) nounwind readnone
%mul27 = fmul float %mul24, %call26
%add28 = fadd float %sub20, %mul27
%call29 = tail call float @dsin(float %add11) nounwind readnone
%mul30 = fmul float %call29, 0x3FF0AB6960000000
%call31 = tail call float @dasin(float %mul30) nounwind readnone
%add32 = fadd float %call31, %add28
ret float %add32
}
declare float @dsin(float) n...
2012 Jul 15
2
[LLVMdev] Issue with Machine Verifier and earlyclobber
On Jul 15, 2012, at 9:20 AM, Borja Ferrer <borja.ferav at gmail.com> wrote:
> Jakob, one more hint, I've placed some asserts around the code you added and noticed that the InlineSpiller::insertReload() function is not being called.
>
> 2012/7/14 Borja Ferrer <borja.ferav at gmail.com>
> Hello Jakob,
>
> I'm still getting the error, I can give you any other
2015 May 21
2
[LLVMdev] How can I remove these redundant copy between registers?
Hi,
I've been working on a Blackfin backend (llvm-3.6.0) based on the previous
one that was removed in llvm-3.1.
llc generates codes like this:
29 p1 = r2;
30 r5 = [p1];
31 p1 = r2;
32 r6 = [p1 + 4];
33 r5 = r6 + r5;
34 r6 = [p0 + -4];
35 r5 *= r6;
36 p1 = r2;
37 r6 = [p1 + 8];
38 p1 = r2;
p1 and r2 are in different register classes.
A p*