Displaying 4 results from an estimated 4 matches for "add16ri".
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add16rr
2009 Dec 07
2
[LLVMdev] How to use property 'isCommutable' in target description file?
...[(set GR16:$dst, (add GR16:$src1, (mul
GR16:$src2, GR16:$src3)))]>
}
How can i tell the system X=A*B + C == X = B*A + C == X=C+A*B == X=C+B*A by
property 'isCommutable'? Is it necessary to do that?
*** Another question: Why set isCommutable = 1 in ADD16rr but NOT set in
ADD16ri?
let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
def ADD16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"add.w\t{$src2, $dst}",
[(set GR16:$dst, (add GR16:$src1, GR16:$src2)),
(implicit SRW)]>;...
2009 Dec 07
0
[LLVMdev] How to use property 'isCommutable' in target description file?
...s it necessary to do that?
Most probably you will need to write a special hook to commute this
instruction. However, everything depends on your target (e.g. if there
is an output register tied to one of the input).
> *** Another question: Why set isCommutable = 1 in ADD16rr but NOT set in
> ADD16ri?
Because all msp430 instructions are two-address, this means that
output register is tied to first input. That's why you cannot swap
operands for reg-imm operations.
--
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University
2009 Dec 08
1
[LLVMdev] How to use property 'isCommutable' in target description file?
...benifit it has if
'isCommuatble=1' in instruction selection, register allocation or other
process?
Regards
2009/12/7, Anton Korobeynikov <anton at korobeynikov.info>:
>
> Hello
>
> > *** Another question: Why set isCommutable = 1 in ADD16rr but NOT set in
> > ADD16ri?
> Because all msp430 instructions are two-address, this means that
> output register is tied to first input. That's why you cannot swap
> operands for reg-imm operations.
>
> --
> With best regards, Anton Korobeynikov
> Faculty of Mathematics and Mechanics, Saint Petersbur...
2009 Sep 18
0
[LLVMdev] Problems with live-ins and live-outs
...OV16ri 10
%R12W<def> = SUB16rr %R12W, %R15W<kill>, %SRW<imp-def>
%R15W<def> = MOV16rr %R12W<kill>
RET %R15W<imp-use,kill>
if.end7: 0xa244cb8, LLVM BB @0xa1f09c0, ID#3:
Live Ins: %R15W %R15B
Predecessors according to CFG: 0xa244c20 (#1)
%R15W<def> = ADD16ri %R15W, 18, %SRW<imp-def>
RET %R15W<imp-use,kill>
return: 0xa244d04, LLVM BB @0xa1efa18, ID#4:
Live Ins: %R15W %R15B
Predecessors according to CFG: 0xa244bd4 (#0)
RET %R15W<imp-use,kill>
# End machine code for f().
*** Bad machine code: Live-in physical register is not liv...