search for: acr_r352_bootstrap

...++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drm/nouveau/nvkm/subdev/secboot/acr_r352.c index a7213542..00095ef8 100644 --- a/drm/nouveau/nvkm/subdev/secboot/acr_r352.c +++ b/drm/nouveau/nvkm/subdev/secboot/acr_r352.c @@ -924,6 +924,19 @@ acr_r352_bootstrap(struct acr_r352 *acr, struct nvkm_secboot *sb) } } + /* reset the PMU if needed */ + if (acr->base.boot_falcon == NVKM_SECBOOT_FALCON_PMU && + !nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_PMU)) { + struct nvkm_pmu *pmu = subdev->device->pmu; + if (pmu) { + ret =...

...gt;func->run_blob(sb, acr->unload_blob); + if (ret) + return ret; + nvkm_debug(&sb->subdev, "HS unload blob completed\n"); + } + + for (i = 0; i < NVKM_FALCON_END; i++) + acr->falcon_state[i] = NON_SECURE; + + sb->wpr_set = false; + + return 0; +} + +static int +acr_r352_bootstrap(struct acr_r352 *acr, struct nvkm_secboot *sb) +{ + int ret; + + if (sb->wpr_set) + return 0; + + /* Make sure all blobs are ready */ + ret = acr_r352_load_blobs(acr, sb); + if (ret) + return ret; + + nvkm_debug(&sb->subdev, "running HS load blob\n"); + ret = sb->func->r...

...13 insertions(+) > > diff --git a/drm/nouveau/nvkm/subdev/secboot/acr_r352.c b/drm/nouveau/nvkm/subdev/secboot/acr_r352.c > index a7213542..00095ef8 100644 > --- a/drm/nouveau/nvkm/subdev/secboot/acr_r352.c > +++ b/drm/nouveau/nvkm/subdev/secboot/acr_r352.c > @@ -924,6 +924,19 @@ acr_r352_bootstrap(struct acr_r352 *acr, struct nvkm_secboot *sb) > } > } > > + /* reset the PMU if needed */ > + if (acr->base.boot_falcon == NVKM_SECBOOT_FALCON_PMU && > + !nvkm_secboot_is_managed(sb, NVKM_SECBOOT_FALCON_PMU)) { > + struct nvkm_pmu *pmu = subdev->devic...

...ffff912df09f80b0 [ 1102.005012] FS:  0000000000000000(0000) GS:ffff912f3ec80000(0000) knlGS:0000000000000000 [ 1102.005012] CS:  0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 1102.005013] CR2: 00007fed2968e020 CR3: 000000028a728004 CR4: 00000000003606e0 [ 1102.005013] Call Trace: [ 1102.005044]  acr_r352_bootstrap+0x16e/0x1d0 [nouveau] [ 1102.005073]  acr_r352_reset+0x21/0x190 [nouveau] [ 1102.005105]  gf100_gr_init_ctxctl_ext+0x59/0x500 [nouveau] [ 1102.005136]  gf100_gr_init_ctxctl+0x19/0x270 [nouveau] [ 1102.005167]  ? gf100_gr_init+0x533/0x570 [nouveau] [ 1102.005181]  nvkm_engine_init+0xa2/0x120 [nouvea...

GP10B is the chip used in Tegra X2 SoCs. This patchset adds support for its base engines after reworking secboot a bit to accomodate its calling convention better. This patchset has been tested rendering simple off-screen buffers using Mesa and yielded the expected result. Alexandre Courbot (15): secboot: allow to boot multiple falcons secboot: pass instance to LS firmware loaders secboot:

This revision includes initial signed PMU firmware support for GM20B (Tegra X1). This PMU code will also be used as a basis for dGPU signed PMU firmware support. With the PMU code, the refactoring of secure boot should also make more sense. ACR (secure boot) support is now separated by the driver version it originates from. This separation allows to run any version of the ACR on any chip,

Hi, just for your information and maybe for some help: with 5.1rc1 and SVM enabled i see the following backtrace [1] when the nouveau card (reverse prime) goes to sleep, for now i have papered over with [2] which leaves me with userspace hangs. Any pointers where to look for the actual culprit? PS: Card is: nouveau 0000:01:00.0: NVIDIA GP106 (136000a1) Greetings, Tobias [1]: BUG: unable

Sending things in a smaller chunks since it makes their reviewing easier. This part part 2/3 of the secboot refactoring/PMU command support patch series. Part 1 was the new falcon library which should be merged soon now. This series is mainly a refactoring/sanitization of the existing secure boot code. It does not add new features (part 3 will). Secure boot handling is now separated by NVIDIA

...ffff88026fdf2420 [ 2.511522] FS: 00007f16362ef8c0(0000) GS:ffff88027ed40000(0000) knlGS:0000000000000000 [ 2.511523] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 2.511523] CR2: 00007f428625dd64 CR3: 00000002735ca000 CR4: 00000000003406e0 [ 2.511524] Call Trace: [ 2.511560] ? acr_r352_bootstrap+0x209/0x21d [nouveau] [ 2.511594] ? acr_r352_reset+0x23/0x1c8 [nouveau] [ 2.511631] ? gf100_gr_init_ctxctl+0x110/0x8ae [nouveau] [ 2.511667] ? gp100_gr_init+0x62c/0x656 [nouveau] [ 2.511694] ? nvkm_engine_init+0x129/0x154 [nouveau] [ 2.511722] ? nvkm_subdev_init+0x114/0x186 [nou...

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

This is a rework of the secure boot code that moves the building of the blob into its own set of source files (and own hooks), making the code more flexible and (hopefully) easier to understand as well. This rework is needed to support more signed firmware for existing and new chips. Since the firmwares in question are not available yet I cannot send the code to manage then, but hopefully the

Last update here: https://lists.freedesktop.org/archives/nouveau/2017-September/028848.html Basically big cleanup, reordering, simplifications and some renaming to make the code easier to read and to review. I also moved some bugfixes to the front so they can be merged prior the other patches. There was also a bug related to the therm daemon triggering a pstate change leading to PMU lockups,

Just wanted to post updated versions of my last series/patches. Reviews welcomed. It would be also nice if we agree on features I should focus upstreaming, so that this work can be better splitted or reordered. Sadly most of my patches depend on the rather big clk subdev rework and I think those patches shows best, why I think this rework is actually needed and makes things much easier to add