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On Mon, Oct 27, 2014 at 6:34 AM, Alexandre Courbot <acourbot at nvidia.com> wrote: > GK20A does not have dedicated VRAM, therefore allocating in VRAM can be > sub-optimal and sometimes even harmful. Set its VRAM domain to > NOUVEAU_BO_GART so all objects are allocated in system memory. > > Signed-off-by: Alexandre Courbot <acourbot at nv...

On 21/05/2015 11:47, Ben Skeggs wrote: > On 21 May 2015 at 16:08, Alexandre Courbot <acourbot at nvidia.com> wrote: >> Add a flag allowing Nouveau to specify that an object should be coherent >> at allocation time. This is required for some class of objects like >> fences which are randomly-accessed by both the CPU and GPU. This flag >> instructs the kernel driver...

LTC device is now required for PGRAPH to work, add it. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- nvkm/engine/device/nve0.c | 1 + 1 file changed, 1 insertion(+) diff --git a/nvkm/engine/device/nve0.c b/nvkm/engine/device/nve0.c index 54ec53bc6252..cdf9147f32a1 100644 --- a/nvkm/engine/device/nve0.c +++ b/nvkm/engine/device/nve0.c @@ -163,6 +163,7 @@ nve0_identify(struct...

...if a failure occurs in nvkm_device_init, even when unloading the module. This can lead to a resources leak (one example is the Tegra interrupt which would never be freed in that case). Fix this by calling nvkm_device_fini in nvkm_device_init's failure path. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/engine/device/base.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drm/nouveau/nvkm/engine/device/base.c b/drm/nouveau/nvkm/engine/device/base.c index b1ba1c782a2b..8ef0ae854038 100644 --- a/drm/nouveau/nvkm/engine/device/base.c +++ b/drm/nouveau/nvkm...

On 3 September 2015 at 16:32, Alexandre Courbot <acourbot at nvidia.com> wrote: > Some devices may not have a PMU. Avoid a NULL pointer dereference in > such cases. > > Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> > --- > drm/nouveau/nvkm/engine/gr/gf100.c | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-...

Op 23-05-15 om 08:45 schreef Alexandre Courbot: > On Fri, May 22, 2015 at 3:23 AM, Martin Peres <martin.peres at free.fr> wrote: >> On 21/05/2015 11:47, Ben Skeggs wrote: >>> On 21 May 2015 at 16:08, Alexandre Courbot <acourbot at nvidia.com> wrote: >>>> Add a flag allowing Nouveau to specify that an object should be coherent >>>> at allocation time. This is required for some class of objects like >>>> fences which are randomly-accessed by both the CPU and GPU. This flag >>>...

Re-pinging Marteen on an email address that still exists :P On Wed, Apr 22, 2015 at 6:08 PM, Alexandre Courbot <gnurou at gmail.com> wrote: > On Sun, Mar 15, 2015 at 5:41 PM, Alexandre Courbot <acourbot at nvidia.com> wrote: >> On 03/14/2015 04:33 AM, Maarten Lankhorst wrote: >>> >>> Hey, >>> >>> Op 13-03-15 om 07:27 schreef Alexandre Courbot: >>>> >>>> Add a flag allowing Nouveau to specify that an object should be coherent >...

On Tue, May 27, 2014 at 12:59 AM, Alexandre Courbot <acourbot at nvidia.com> wrote: > GK20A is mostly compatible with GK104, but features a new 3D > class. Add it to the relevant header and use it when GK20A is > detected. > > Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> > --- > src/gallium/drivers/nouveau/nv_object...

On Mon, Apr 21, 2014 at 2:02 AM, Alexandre Courbot <acourbot at nvidia.com> wrote: > Pad the microcode to a multiple of 0x40 bytes, otherwise firmware will bytes or u32's? From the code, I'm guessing the latter. (Similar concern about comment in the code.) > fail to run from non-prepadded firmware files. > > Signed-off-by: Alexandre...

Two trivial PMU-related fixes for Tegra: - Add a dummy func member to GK20A, since nvkm_pmmu_pgob() unconditionally dereferences it - Check whether a PMU actually exists before calling nvkm_pmmu_pgob(). During early bringup we are likely to not have a PMU Alexandre Courbot (2): pmu/gk20a: add dummy func gr/gf100: do not assume a PMU is present drm/nouveau/nvkm/engine/gr/gf100.c | 3 ++-

...s like >> fences which are randomly-accessed by both the CPU and GPU. This flag >> instructs the kernel driver to make sure the object remains coherent >> even on architectures for which coherency is not guaranteed by the bus. >> >> Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> > I don't see a problem with this patch, but similar patches to intel to libdrm have been shot down when the changes weren't in an official kernel yet, so I think this should wait until the change is at least in drm-next. ;-) Sounds good. I will ping you again once the...

...rote: > Op 15-05-15 om 09:11 schreef Alexandre Courbot: >> Re-pinging Marteen on an email address that still exists :P >> >> On Wed, Apr 22, 2015 at 6:08 PM, Alexandre Courbot <gnurou at gmail.com> wrote: >>> On Sun, Mar 15, 2015 at 5:41 PM, Alexandre Courbot <acourbot at nvidia.com> wrote: >>>> On 03/14/2015 04:33 AM, Maarten Lankhorst wrote: >>>>> Hey, >>>>> >>>>> Op 13-03-15 om 07:27 schreef Alexandre Courbot: >>>>>> Add a flag allowing Nouveau to specify that an object should be coh...

On 3 September 2015 at 17:11, Alexandre Courbot <gnurou at gmail.com> wrote: > On Thu, Sep 3, 2015 at 4:08 PM, Ben Skeggs <skeggsb at gmail.com> wrote: >> On 3 September 2015 at 16:32, Alexandre Courbot <acourbot at nvidia.com> wrote: >>> Some devices may not have a PMU. Avoid a NULL pointer dereference in >>> such cases. >>> >>> Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> >>> --- >>> drm/nouveau/nvkm/engine/gr/gf100.c | 3 ++- &gt...

On Mon, Apr 21, 2014 at 2:02 AM, Alexandre Courbot <acourbot at nvidia.com> wrote: > Skip the creation of a software channel for GK20A as software methods > are not yet supported. How is GK20A different from a nvc0+ card that lacks PDISPLAY (like all the 3D Controller ones, and I guess even some that come up as VGA controller in PCI but don't h...

...e. This is required for some class of objects like fences which are randomly-accessed by both the CPU and GPU. This flag instructs the kernel driver to make sure the object remains coherent even on architectures for which coherency is not guaranteed by the bus. Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> --- Changes since v1: None, just added Martin so he can merge the patch. R-b and A-b wanted. :) include/drm/nouveau_drm.h | 1 + nouveau/abi16.c | 3 +++ nouveau/nouveau.h | 1 + 3 files changed, 5 insertions(+) diff --git a/include/drm/nouveau_drm.h b/include...

On Mon, May 19, 2014 at 04:10:57PM +0900, Alexandre Courbot wrote: > From: Lucas Stach <dev at lynxeye.de> > > Signed-off-by: Lucas Stach <dev at lynxeye.de> > [acourbot at nvidia.com: make conditional and platform-friendly] > Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> Perhaps having a propery commit message here would be good. > diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c [...] > +#ifdef...

...ason or another don't have the PMU hooked up. That should be fixed in its own right, but that's a separate matter. The issue was introduced in commit e2ca4e7d6e (drm/nouveau/pmu: convert to new-style nvkm_subdev) commit 579b7c58215329803ce184704463de09f0f310ac Author: Alexandre Courbot <acourbot at nvidia.com> Date: Thu Sep 3 17:39:52 2015 +0900 drm/nouveau/pmu: do not assume a PMU is present Some devices may not have a PMU. Avoid a NULL pointer dereference in such cases by checking whether the pointer given to nvkm_pmu_pgob() is valid. Signed-off-by: Alexandre...

On Mon, Mar 24, 2014 at 6:42 PM, Alexandre Courbot <acourbot at nvidia.com> wrote: > Pad the microcode to a multiple of 0x40, otherwise firmware will fail to > run from non-prepadded firmware files. > > Signed-off-by: Alexandre Courbot <acourbot at nvidia.com> > --- > drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c | 4 ++++ >...

The following 2 patches make it possible to run Mesa programs on GK20A (Tegra K1). GK20A is very similar to GK104, but uses a new (backward-compatible) 3D class as well as the same ISA as GK110 (SM35). Taking these differences into account is sufficient to successfully render simple off-screen buffers. Alexandre Courbot (2): nvc0: add GK20A 3D class nvc0: use SM35 ISA with GK20A

Here are a few small fixes for issues we found while implementing support for GM20B. The first two are specific to Tegra/GK20A, but the last 3 patches may have a broader (hopefully beneficial) effect. Note that the newly introduced gf100_gr_wait_idle() function on patch 5/5 is exported on purpose. GK20A and GM20B drivers will soon make use of it. Ben, since you seemed to like these changes, a