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Motivation At the moment, when targeting armv7a, clang defaults to generate code as if -mcpu=cortex-a8 was specified. When targeting armv8a, it defaults to generate code as if -mcpu=cortex-a53 was specified. This leads to surprising code generation, by the compiler optimizing for a specific micro-architecture, whereas the intent from the user was probably to generate code that is

Thanks for everyone giving their feedback! I saw pretty unanimous support for making -mcpu=generic the default and making -mcpu=generic schedule for an in-order CPU (Cortex-A8 in this case). I'll be making those changes shortly. I think the comments also make clear that it's less obvious whether we'd want -mcpu=native to become a default. It's probably good for some use cases, but

I was working with the rmetrics portfolioBacktesting function and dug into the code to try to find why my formula with 113 items, i.e. A1 thru A113, was being truncated and I only get 85 items, not 113. Is it due to a string length limitation in R or is it a bug in the strsplit or gsub functions, or in my string? I'd very much appreciate any suggestions ============Input script:

Hello All, I need some help with respect to cross compiling for ARM. While trying to cross compile for the ARM target, I am hitting some errors. I need some help in this. I use the following command to cross compile for ARM Cortex A72 (ARM v8-a), 64 bit architecture: *cmake -v CC='clang' CXX='clang++' -DCMAKE_C_COMPILER=../build_directory_llvm/bin/clang

Hello, I’m using NXP layerscape Arch (A53/A72), and I want to use NE 10 Project library , and llvm compiler 3.8.1.1 (https://projectne10.github.io/Ne10/) <https://projectne10.github.io/Ne10/> When compiling the project file I get the following errors : ./NE10_abs.asm.s:59:9: error: unrecognized instruction mnemonic vmov s2, r3 ^ ../NE10_abs.asm.s:62:9: error:

Summary ======= I'm planning on adjusting SimplifyCFG so that it doesn't turn two-entry phi nodes into selects until later in the pass pipeline, to give passes which can understand phis but not selects more opportunity to optimize. The thing I'm trying to do which made me think of doing this is described below, but from the benchmarking I've done it looks like this is overall a

Actually its the ccflags I am using with that particular distro. -mcpu=cortex-a72 -mfloat-abi=hard -mfpu=neon-fp-armv8 -mneon-for-64bits Which is optimised for pi4 isn’t liked. Also without ccflag=”” configure: error: No 16 bit type found on this platform! ./configure --enable-neon --libdir=/usr/lib/aarch64-linux-gnu I dropped down to ubuntu 18.04 and the same errors occur. I have a

Hi, Arm have recently announced the v8.1-M architecture specification for our next generation microcontrollers. The architecture includes vector extensions (MVE) and support for low-overhead branches (LoB), which can be thought of a style of hardware loop. Hardware loops aren't new to LLVM, other backends (at least Hexagon and PPC that I know of) also include support. These implementations

When I pass an empty string for cpu and features to createTargetMachine, and then use LLVMGetTargetMachineCPU() and LLVMGetTargetMachineFeatureString() to get the strings back, they are still empty. Is there a way to have llvm compute the effective cpu/features string, and provide it so that I can inspect it? I'm trying to figure out how the cpu/features string that I am explicitly passing,

I'm concerned that we're focusing on one side of this.  Let me point out a few concerns w/changing the canonical form here: 1. LICM does not know how to hoist or sink regions.  It does know how to hoist and sink selects. 2. InstCombine has limited support for triangles/diamonds, but fairly extensive support for selects. 3. EarlyCSE and GVN do not know how to eliminate fully

...Mime-Version: 1.0 (Apple Message framework v481) From: Michael Maskalans <mindless at cif.rochester.edu> To: <problem at cif.rochester.edu> Content-Transfer-Encoding: 7bit In-Reply-To: <003501c1e6f0$d4859bb0$ef441842 at yi0b4plk53mjqz> Message-Id: <71B00250-539A-11D6-A72E-00039303ECDC at cif.rochester.edu> X-Mailer: Apple Mail (2.481) Content-Length: 301 Status: RO X-UID: 326402 ) ========================== It looks like dovecot really isn't sending any information for message #1, starting right off at message #2. The headers it gives for mess...

> On Aug 15, 2018, at 10:57 PM, Hal Finkel via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > > On 08/15/2018 02:38 PM, Philip Reames via llvm-dev wrote: >> I'm concerned that we're focusing on one side of this. Let me point out a few concerns w/changing the canonical form here: >> >> LICM does not know how to hoist or sink regions. It does know

Hi All I downloaded the binary package of Samba 2.2.2 on Friday from one of the Samba mirror sites, I think Belgium, and installed it on a Sun E450 running Solaris 2.6. Today everything has fallen flat on its face. Unfortunately I am on holiday this week so not able to deal with the problem directly, but via telephone calls. Apparently what is happening is that smbd is gobbling up all the

Hello R users, For the last few days I am struggling with the following task: my data.frame: A1 A2 A3 B1 B2 B3 58.81 53.292 54.501 13.013 17.39 19.407 56.02 56.251 54.033 20.099 13.15 10.411 55.376 53.099 57.625 13.396 21.031 13.22 58.584 53.194 54.218 13.038 16.854 19.289 55.7 55.921 53.847 19.942 13.153 9.828 55.093 52.934

https://bugzilla.mindrot.org/show_bug.cgi?id=3639 Bug ID: 3639 Summary: server thread aborts during client login after receiving SSH2_MSG_KEXINIT Product: Portable OpenSSH Version: 9.2p1 Hardware: ARM OS: Linux Status: NEW Severity: critical Priority: P5 Component: