search for: a32

--- silk/macros.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/silk/macros.h b/silk/macros.h index 1ba614a..e1e05b9 100644 --- a/silk/macros.h +++ b/silk/macros.h @@ -48,14 +48,14 @@ POSSIBILITY OF SUCH DAMAGE. /* (a32 * (opus_int32)((opus_int16)(b32))) >> 16 output have to be 32bit int */ #if OPUS_FAST_INT64 -#define silk_SMULWB(a32, b32) (((a32) * (opus_int64)((opus_int16)(b32))) >> 16) +#define silk_SMULWB(a32, b32) ((opus_int32)(((a32) * (opus_int64)((opus_int16)(b32))) >...

...6 @@ POSSIBILITY OF SUCH DAMAGE. #define opus_unlikely(x) (!!(x)) #endif -/* Set this if opus_int64 is a native type of the CPU. */ -#define OPUS_FAST_INT64 (defined(__x86_64__) || defined(__LP64__) || defined(_WIN64)) - /* This is an OPUS_INLINE header file for general platform. */ /* (a32 * (opus_int32)((opus_int16)(b32))) >> 16 output have to be 32bit int */ -- 2.4.9 (Apple Git-60)

...0 @@ POSSIBILITY OF SUCH DAMAGE. #define opus_unlikely(x) (!!(x)) #endif +/* Set this if opus_int64 is a native type of the CPU. */ +#define OPUS_FAST_INT64 (defined(__x86_64__) || defined(__LP64__) || defined(_WIN64)) + /* This is an OPUS_INLINE header file for general platform. */ /* (a32 * (opus_int32)((opus_int16)(b32))) >> 16 output have to be 32bit int */ -#if defined(__x86_64__) || defined(__LP64__) || defined(_WIN64) +#if OPUS_FAST_INT64 #define silk_SMULWB(a32, b32) (((a32) * (opus_int64)((opus_int16)(b32))) >> 16) #else #define silk_SMULWB(a32, b32)...

--- configure.ac | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/configure.ac b/configure.ac index f52d2c2..e1a6e9b 100644 --- a/configure.ac +++ b/configure.ac @@ -190,7 +190,7 @@ AC_ARG_ENABLE([rtcd], [enable_rtcd=yes]) AC_ARG_ENABLE([intrinsics], - [AS_HELP_STRING([--disable-intrinsics], [Disable intrinsics optimizations for ARM(float) X86(fixed)])],, +

...63 levels). I would like to associate each name with a particular Type (coded as 1,2,3,4,H or H1) in a second column. Is it possible to do a lookup table of associations (i.e. A23 is of type 1, A13 is of type 3 ...) so as to fill up automatically the $Type column. df() $Source $Type A23 A24 A9 A32 A25 A14 A10 A12 A11 A13 G Alternative solutions are also welcome. Thanks in advance P.S. I found a discussion mentioning match() and %in% but it does not seem adapted. -- Nikola Markov Inserm U 846 Stem cells and brain research institute 18 av Du Doyen Lepine 69500 Bron France

...OSE[10393] logger.c: -- Started music on hold, class 'default', on channel 'Zap/32-1' Feb 2 13:47:20 DEBUG[10393] channel.c: Scheduling timer at 160 sample intervals Feb 2 13:47:20 VERBOSE[10393] logger.c: -- outgoing agentcall, to agent '300', on 'Local/205@default-a32e,1' Feb 2 13:47:20 VERBOSE[10393] logger.c: -- Called Agent/300 Feb 2 13:47:20 VERBOSE[10395] logger.c: -- Executing Dial("Local/205@default-a32e,2", "SIP/205|30|tT") in new stack Feb 2 13:47:20 DEBUG[10395] chan_sip.c: Outgoing Call for 205 Feb 2 13:47:20 VERBOSE[10395...

...344cf..fd9ad5d 100644 --- a/silk/macros.h +++ b/silk/macros.h @@ -32,6 +32,10 @@ POSSIBILITY OF SUCH DAMAGE. #include "config.h" #endif +#ifdef ARM5E_ASM +#include "macros_arm5e.h" +#else /* Generic macro */ + /* This is an inline header file for general platform. */ /* (a32 * (opus_int32)((opus_int16)(b32))) >> 16 output have to be 32bit int */ @@ -134,5 +138,7 @@ static inline opus_int32 silk_CLZ32(opus_int32 in32) (*((Matrix_base_adr) + ((row)+(M)*(column)))) #endif +#endif + #endif /* SILK_MACROS_H */ diff --git a/silk/macros_arm5e.h b/silk/macros_...

--- silk/macros.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/silk/macros.h b/silk/macros.h index e1e05b9..7cefedc 100644 --- a/silk/macros.h +++ b/silk/macros.h @@ -61,7 +61,11 @@ POSSIBILITY OF SUCH DAMAGE. #endif /* (a32 * (b32 >> 16)) >> 16 */ +#if OPUS_FAST_INT64 +#define silk_SMULWT(a32, b32) ((opus_int32)(((a32) * (opus_int64)((b32) >> 16)) >> 16)) +#else #define silk_SMULWT(a32, b32) (((a32) >> 16) * ((b32) >> 16) + ((((a32) & 0x0000FFFF) * ((b32)...

Hi, A64 versus A32/T32 code generation is controlled by the -target option which I don’t believe is under discussion here. James On 18 May 2016, at 13:17, Bruce Hoult <bruce at hoult.org<mailto:bruce at hoult.org>> wrote: Note that armv8a modifies the A32 and T32 instruction sets, and is therefore an im...

Hi everyone, I'm a member engineer of linaro's llvm team,coming from Spreadtrum.I am a new person on LLVM.Now I'm writing a Target Parser for AArch64,so options parsing of AArch64 about cpu & arch & fpu can be summary to one place. In the TargetParser,we assume "aarch64" and "arm64" are synonyms of armv8a(as they are only for armv8a,people usually do

...columns of a symmetrical matrix that represents ecological or actual distances between objects in space. The permutation is of the type used in a Mantel test. Specifically, the permutation has to accomplish something like this: Original matrix addresses: a11 a12 a13 a21 a22 a23 a31 a32 a33 Example permutation a22 a23 a21 a32 a33 a31 a12 a13 a11 that is relative positions of rows and columns are conserved in the permutation. Basically, I have been doing this in a "for" loop by (1) permuting the raw data vector using "sample", (2) generating...

CentOS Errata and Security Advisory CESA-2007:0465 pam security update for CentOS 3 i386: https://rhn.redhat.com/errata/RHSA-2007-0465.html The following updated file has been uploaded and is currently syncing to the mirrors: i386: updates/i386/RPMS/cdrecord-2.01.0.a32-0.EL3.6.i386.rpm updates/i386/RPMS/cdrecord-devel-2.01.0.a32-0.EL3.6.i386.rpm updates/i386/RPMS/mkisofs-2.01.0.a32-0.EL3.6.i386.rpm updates/i386/RPMS/pam-0.75-72.i386.rpm updates/i386/RPMS/pam-devel-0.75-72.i386.rpm addons/i386/RPMS/cdda2wav-2.01.0.a32-0.EL3.6.i386.rpm source: updates/SRPMS/cdrto...

CentOS Errata and Security Advisory CESA-2007:0465 pam security update for CentOS 3 x86_64: https://rhn.redhat.com/errata/RHSA-2007-0465.html The following updated file has been uploaded and is currently syncing to the mirrors: x86_64: updates/x86_64/RPMS/cdrecord-2.01.0.a32-0.EL3.6.x86_64.rpm updates/x86_64/RPMS/cdrecord-devel-2.01.0.a32-0.EL3.6.x86_64.rpm updates/x86_64/RPMS/mkisofs-2.01.0.a32-0.EL3.6.x86_64.rpm updates/x86_64/RPMS/pam-0.75-72.i386.rpm updates/x86_64/RPMS/pam-0.75-72.x86_64.rpm updates/x86_64/RPMS/pam-devel-0.75-72.i386.rpm updates/x86_64/RPMS/pam-de...

...th limitation in R or is it a bug in the strsplit or gsub functions, or in my string? I'd very much appreciate any suggestions ============Input script: backtestFormula<-SPX~A1+A2+A3+A4+A5+A6+A7+A8+A9+A10+A11+A12+A13+A14+A15+A16+A17+A18+A19+A20+A21+A22+A23+A24+A25+A26+A27+A28+A29+A30+A31+A32+A33+A34+A35+A36+A37+A38+A39+A40+A41+A42+A43+A44+A45+A46+A47+A48+A49+A50+A51+A52+A53+A54+A55+A56+A57+A58+A59+A60+A61+A62+A63+A64+A65+A66+A67+A68+A69+A70+A71+A72+A73+A74+A75+A76+A77+A78+A79+A80+A81+A82+A83+A84+A85+A86+A87+A88+A89+A90+A91+A92+A93+A94+A95+A96+A97+A98+A99+A100+A101+A102+A103+A104+A105+A...

Dear all, suppose I have a vector with elements as: Vec <- c(2,3,4,5,6) Now I want to have all possible combination of length 3 using those elements and without any repetition. Like, I want to have 1 possibility like 2-3-4 but not 3-2-4. Can somebody guide me how to achieve that in R? Thanks for your help.

...entos.s390.rpm updates/s390/RPMS/autofs-4.1.3-130.s390.rpm updates/s390/RPMS/bash-2.05b-41.4.centos.0.s390.rpm updates/s390/RPMS/bzip2-1.0.2-11.EL3.1.s390.rpm updates/s390/RPMS/bzip2-devel-1.0.2-11.EL3.1.s390.rpm updates/s390/RPMS/bzip2-libs-1.0.2-11.EL3.1.s390.rpm updates/s390/RPMS/cdda2wav-2.01.0.a32-0.EL3.2.s390.rpm updates/s390/RPMS/cdrecord-2.01.0.a32-0.EL3.2.s390.rpm updates/s390/RPMS/cdrecord-devel-2.01.0.a32-0.EL3.2.s390.rpm updates/s390/RPMS/centos-release-3-5.3.s390.rpm updates/s390/RPMS/chkconfig-1.3.13.2-0.3.s390.rpm updates/s390/RPMS/control-center-2.2.0.1-15.s390.rpm updates/s390/RP...

...ddress (i have forgotten what this does, could be wrong even, way over twenty years and practically no wire experience, no interface identifier support) // is it IPv4 (RFC's 1884, 2133)? if( #if(SF_64BIT) m_ip6.a64[0] == 0 #else m_ip6.a32[0] == 0 && m_ip6.a32[1] == 0 #endif && m_ip6.a16[4] == 0 // a32[2] == 0 || a32[2] == NTOH(0x0000FFFF) ) { ui4 i = m_ip6.a32[3]; m_ip4 = i; switch(m_ip6.a16[5]) { c...

Hi, so here it is, LZ4 compression method inside btrfs. The patchset is based on top of current Chris'' for-linus + Andi''s snappy implementation + the fixes from Li Zefan. Passes xfstests and stresstests. I haven''t measured performance on wide range of hardware or workloads, rather wanted to publish the patches before I get distracted again. I''d like to ask

WARNING: This is not compatible with the previous lz4 patchset. If you''re using experimental compression that isn''t in mainline kernels, be prepared to backup and restore or decompress before upgrading, and have backups in case it eats data (which appears not to be a problem any more, but has been during development). These patches add lz4 and lz4hc compression

Hi, On Sun, Jul 14, 2024 at 10:25:46AM +0100, Brian Candler wrote: > On 14/07/2024 03:49, Steffen Nurpmeso wrote: > > I have read > > > > https://datatracker.ietf.org/doc/html/draft-cmetz-v6ops-v4mapped-api-harmful-01 > > > > but as an application developer i find it ugly not to be able to > > "simply do it", and get back a mapped address.