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...The behaviour I’m talking about I’ve actually pinned down to CodeGenPrepare not working too well with ISA’s that don’t have a good scaled load. I have a patch to fix it that is going through performance testing now. Your testcase seems specific to x86 – for aarch64 we get the rather spiffy: _Z3fooPii: // @_Z3fooPii // BB#0: // %entry add w8, w1, #1 // =1 add w9, w1, #2 // =2 ldr w8, [x0, w8, sxtw #2] ldr w9,...

...ually pinned down to CodeGenPrepare not working too well with ISA’s that don’t have a good scaled load. I have a patch to fix it that is going through performance testing now. > > > > Your testcase seems specific to x86 – for aarch64 we get the rather spiffy: > > > > _Z3fooPii: // @_Z3fooPii > > // BB#0: // %entry > > add w8, w1, #1 // =1 > > add w9, w1, #2 // =2 > > ldr w8, [x0, w8, sxtw...

HI James, Thanks for your reply and hints on what can be done for the Aarch64 backend optimization for llvm We have SPEC license and v8 hardware. So I will start looking into it warm regards Manjunath On Wed, Jun 25, 2014 at 8:42 PM, James Molloy <james.molloy at arm.com> wrote: > Hi Manjunath, > > At the time of writing that status we had only done our initial analysis. >