search for: _rr

...me spent on polling were limited >> through a module parameter. To avoid block rx, the loop will end it >> there's new other works queued on vhost so in fact socket receive >> queue is also be polled. >> >> busyloop_timeout = 50 gives us following improvement on TCP_RR test: >> >> size/session/+thu%/+normalize% >> 1/ 1/ +5%/ -20% >> 1/ 50/ +17%/ +3% > > Is there a measureable increase in cpu utilization > with busyloop_timeout = 0? And since a netperf TCP_RR test is involved, be careful about what netperf...

...lman/listinfo/llvm-dev > I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details: defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>; multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> { def _rr : SF_RR<op2Val, asmstr, Cond>; def _ri : SF_RI<op2Val, asmstr, Cond>; } class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond> : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB), !strconcat(asmstr, "\t$rA, $rB"), [(Escalasetflag (i32 GPR:$...

Hi Guys, In LLVM codegen, a typical binary operation instruction is defined something like below: " def _rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b), "xor.pred \t$dst, $a, $b;", [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>; “ which takes two inputs and write the result to the $dst register. Then how to define a binary instruction which...

In BPF, an ADD instruction is defined as a 2 register instruction: 0x0f. add dst, src. dst += src In BPFInstrInfo.td this kind of ALU instruction is defined with: def _rr : ALU_RR<BPF_ALU64, Opc, (outs GPR:$dst), (ins GPR:$src2, GPR:$src), "$dst "#OpcodeStr#" $src", [(set GPR:$dst, (OpNode i64:$src2, i64:$src))]>; How does tablegen+codegen ensure that dst and src2...

...wants to put two old good ISA NICS into a home where they will be cared for and appreciated, send me an email with details, if config diskette available (even if off the net), price, etc. I'll pay shipping too. Remove the underscores in the following address. w_ild-_bi_ll_ at _tra_id._rr._c_o_m TIA

...ere limited > >>through a module parameter. To avoid block rx, the loop will end it > >>there's new other works queued on vhost so in fact socket receive > >>queue is also be polled. > >> > >>busyloop_timeout = 50 gives us following improvement on TCP_RR test: > >> > >>size/session/+thu%/+normalize% > >> 1/ 1/ +5%/ -20% > >> 1/ 50/ +17%/ +3% > > > >Is there a measureable increase in cpu utilization > >with busyloop_timeout = 0? > > And since a netperf TCP_RR test is i...

...ing. The maximum time spent on polling were limited > through a module parameter. To avoid block rx, the loop will end it > there's new other works queued on vhost so in fact socket receive > queue is also be polled. > > busyloop_timeout = 50 gives us following improvement on TCP_RR test: > > size/session/+thu%/+normalize% > 1/ 1/ +5%/ -20% > 1/ 50/ +17%/ +3% Is there a measureable increase in cpu utilization with busyloop_timeout = 0? > Signed-off-by: Jason Wang <jasowang at redhat.com> We might be able to shave off the minor regr...

...ing. The maximum time spent on polling were limited > through a module parameter. To avoid block rx, the loop will end it > there's new other works queued on vhost so in fact socket receive > queue is also be polled. > > busyloop_timeout = 50 gives us following improvement on TCP_RR test: > > size/session/+thu%/+normalize% > 1/ 1/ +5%/ -20% > 1/ 50/ +17%/ +3% Is there a measureable increase in cpu utilization with busyloop_timeout = 0? > Signed-off-by: Jason Wang <jasowang at redhat.com> We might be able to shave off the minor regr...

...> I think I understand it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details: > > defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>; > > multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> { > def _rr : SF_RR<op2Val, asmstr, Cond>; > def _ri : SF_RI<op2Val, asmstr, Cond>; > } > > class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond> > : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB), > !strconcat(asmstr, "\t$rA, $rB"), >...

...e = "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); } multiclass BinaryOp<SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1, Operand lit> { def _rr: ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconcat(op.Text, " $dst, $src0, $src1"), [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; def _ri : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, lit:$src1), "and $dst, $src0, $src...

...nexthop via X.X.X.X dev vlan110 weight 1 nexthop via Y.Y.Y.Y dev vlan120 weight 1 So it looks quite good. However, all traffic is routed via Y.Y.Y.Y, no matter what I do. I can increase the weight of X.X.X.X, load and unload the various multipath kernel modules (_rr, _random, _wrandom, and _drr), flush the cache routing table, delete and re-add the route, but still traffic is only sent to X.X.X.X If I reverse the order of the nexthops on the command line, that is: ip route add table 101 default \ nexthop via Y.Y.Y.Y nexthop via X.X.X.X...

...e = "AMDIL"; dag OutOperandList = outs; dag InOperandList = ins; let Pattern = pattern; let AsmString = !strconcat(asmstr, "\n"); } multiclass BinaryOp<SDNode OpNode, RegisterClass dReg, RegisterClass sReg0, RegisterClass sReg1, Operand lit> { def _rr: ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), !strconcat(op.Text, " $dst, $src0, $src1"), [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; def _ri : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, lit:$src1), "and $dst, $src0, $src...

...ter which one, and create custom nodes if it meets that condition. But I think a better solution would be to add pattern matching rules for all of them systematically. IMO it's cleaner and easier to maintain. You can use multiclasses : multiclass Inst< node op, string opc> { def _rr : Instruction<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), "!strcat(opc, " $dst, $src1, $src2")", [(set $dst, (op GPR32:$src1, GPR32:$src2))]>; def _fneg_rr : Instruction<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), &...

...ndList = outs; > dag InOperandList = ins; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); > } > multiclass BinaryOp<SDNode OpNode, RegisterClass dReg, > RegisterClass sReg0, RegisterClass sReg1, Operand lit> > { > def _rr: ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), > !strconcat(op.Text, " $dst, $src0, $src1"), > [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; > def _ri : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, lit:$src1), > "an...

I've been unable to come up with the TableGen recipe to match a negated operand. My target asm syntax allows the following transform: FNEG r8, r5 MUL r6, r8, r9 to MUL r6, -r5, r9 Is there a Pattern<> syntax that would allow matching *any* opcode (or even some subset), not just MUL, with a FNEG'd operand? I expect I can define a PatFrag: def fneg_su : PatFrag<(ops

...ndList = outs; > dag InOperandList = ins; > let Pattern = pattern; > let AsmString = !strconcat(asmstr, "\n"); > } > multiclass BinaryOp<SDNode OpNode, RegisterClass dReg, > RegisterClass sReg0, RegisterClass sReg1, Operand lit> > { > def _rr: ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, sReg1:$src1), > !strconcat(op.Text, " $dst, $src0, $src1"), > [(set dReg:$dst, (OpNode sReg0:$src0, sReg1:$src1))]>; > def _ri : ILFormat<op, (outs dReg:$dst), (ins sReg0:$src0, lit:$src1), > "an...

...O_MultSrc<op0t, SpecialReg>.outsDefault, IO_MultSrc<op0t, SpecialReg>.insDefault>; ... } multiclass TwoSrcOneDestSpec<bits<5> subOpcode, string opcodeStr> { defm _dds: MultSrc1Spec<subOpcode, 0b10, opcodeStr, SpecialReg>; ... defm _rr: MultSrc1Spec<subOpcode, 0b11, opcodeStr, GPReg>; } defm ADD : TwoSrcOneDestSpec<0b10000, "add">; I currently get the error "Undefined reference:'ADDanonymous_545'" when I try to generate. Any advice would be greatly appreciated, even if that advice is &...

...nd it. But looks like I have everything labelled properly. Maybe I missed something. Here are more details: > > > > defm SFEQ : SF<0x0, "l.sfeq", Escala_CC_EQ>; > > > > multiclass SF<bits<5> op2Val, string asmstr, PatLeaf Cond> { > > def _rr : SF_RR<op2Val, asmstr, Cond>; > > def _ri : SF_RI<op2Val, asmstr, Cond>; > > } > > > > class SF_RR<bits<5> op2Val, string asmstr, PatLeaf Cond> > > : InstRR<0x9, (outs), (ins GPR:$rA, GPR:$rB), > > !strconcat(asmstr, &qu...

I've added a new register class to my target, but haven't used any of the new registers in any of the instructions. However when I compile llvm I get the following error: In SFEQ_ri: Could not infer all types in pattern Curiously all the instructions where this error occurs are the set flag instructions (flags like zero, less than, greater than etc). Would anyone be able to figure out

...lly <cameron.mcinally at nyu.edu> wrote: > On Mon, Jun 16, 2014 at 4:51 PM, kewuzhang <kewu.zhang at amd.com> wrote: >> Hi Guys, >> >> In LLVM codegen, >> a typical binary operation instruction is defined something like below: >> >> " def _rr: NVPTXInst<(outs Int1Regs:$dst), (ins Int1Regs:$a, Int1Regs:$b), >> "xor.pred \t$dst, $a, $b;", >> [(set Int1Regs:$dst, (OpNode Int1Regs:$a, Int1Regs:$b))]>; >> “ >> >> which takes two inputs and write the result to the $dst register. &gt...