search for: _mask

xentrace, setsize and the hypervisor don''t seem to be on the same page. If tracing is not enabled, the hypercall will only allow TBUF_SET_SIZE and TBUF_ENABLE. However, set_size calls TBUF_GET_INFO, and xentrace wants to call TBUF_SET_EVT_MASK and TBUF_SET_CPU_MASK before calling TBUF_ENABLE. I don''t see any reason not to call SET_*_MASK and GET_INFO if tracing is not enabled. If the buffer hasn''t been allocated yet, GET_INFO should just return something invalid in the mfn field. Anyone calling should check this va...

..._id != ACPI_ADR_SPACE_SYSTEM_MEMORY) { printk(KERN_WARNING PREFIX "HPET timers must be located in " "memory.\n"); return -1; --- a/xen/arch/x86/srat.c +++ b/xen/arch/x86/srat.c @@ -396,7 +396,8 @@ void __init srat_parse_regions(u64 addr) return; srat_region_mask = fill_mask(addr - 1); - acpi_table_parse_srat(ACPI_SRAT_MEMORY_AFFINITY, srat_parse_region, 0); + acpi_table_parse_srat(ACPI_SRAT_TYPE_MEMORY_AFFINITY, + srat_parse_region, 0); for (mask = srat_region_mask, i = 0; mask && i < e820.nr_map; i++) { if (e820.map[i].type != E8...

Patch 1 fixes nva3 bailing due to not finding the right ramcfg Patch 2 is a resend rebased on 3.17.0-rc4 for setting the vblank period Patch 3-5 handle writes to per-partition registers, for which NVA3 does not have special broadcast regs available. Patch 6 removes local structs from NVA3 reclocking in favour of the already existing "ram->base." variables, like in NVE0 As always,

Hello, could you please have a look at this code posted on godbolt.org: https://godbolt.org/z/O-O-Q7 The problem is that inside the compute function, only the first loop vectorizes while the rest copies of it don't. But if I remove any of the for loops, then the rest vectorize successfully. Could you please confirm that this is a bug, otherwise give me more insight on why the vectorization

...<nbd_can_fua(3)> returned false). If clear, this flag relies on the server to reject unexpected commands. +=item C<LIBNBD_STRICT_FLAGS> = 2 + +If set, this flag rejects client requests that attempt to set a +command flag not recognized by libnbd (those outside of +C<LIBNBD_CMD_FLAG_MASK>). If clear, this flag passes on unknown +flags to the server. One possible reason to relax this strictness +knob is to send C<LIBNBD_CMD_FLAG_FUA> on a read command (libnbd +normally prevents that, but the NBD protocol allows it to succeed); +however, it is also possible that sending an...

...se). If clear, this flag relies on the > server to reject unexpected commands. > > +=item C<LIBNBD_STRICT_FLAGS> = 2 > + > +If set, this flag rejects client requests that attempt to set a > +command flag not recognized by libnbd (those outside of > +C<LIBNBD_CMD_FLAG_MASK>). If clear, this flag passes on unknown > +flags to the server. One possible reason to relax this strictness > +knob is to send C<LIBNBD_CMD_FLAG_FUA> on a read command (libnbd > +normally prevents that, but the NBD protocol allows it to succeed); > +however, it is also poss...

...heck parameters are valid. *) - let print_flags_check n { flag_prefix } = + let print_flags_check n { flag_prefix; flags } subset = let value = match errcode with | Some value -> value | None -> assert false in - pr " if (unlikely ((%s & ~LIBNBD_%s_MASK) != 0)) {\n" n flag_prefix; + let mask = match subset with + | Some [] -> "0" + | Some subset -> + let v = ref 0 in + List.iter ( + fun (flag, i) -> + if List.mem flag subset then v := !v lor i + ) fl...

In v2: - now based on my proposal to add LIBNBD_SHUTDOWN_IMMEDIATE - four flags instead of two: STRICT_FLAGS is new (patch 4), and STRICT_BOUNDS is separate from STRICT_ZERO_SIZE (patch 5) - various refactorings for more shared code and less duplication Eric Blake (5): api: Add xxx_MASK constant for each Flags type generator: Refactor filtering of accepted OFlags api: Add nbd_set_strict_mode api: Add STRICT_FLAGS to set_strict_mode api: Add STRICT_BOUNDS/ZERO_SIZE to nbd_set_strict_mode docs/libnbd.pod | 7 + lib/internal.h...

Joe Perches (2): drm: Use pr_cont where appropriate gpu: drm: Convert printk(KERN_<LEVEL> to pr_<level> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +- drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_atpx_handler.c | 4 +- drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 4 +-

...quot;REGISTER: " #reg " : 0x%08X\n", \ + amdgpu_mm_rreg(adev, (reg), false)) #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c index 857ba0897159..3889486f71fe 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c @@ -74,9 +74,9 @@ static void amdgpu_afmt_calc_cts(uint32_t clock,...

This round implements all of the review comments from V2 and all patches are now acked. Unless there are any objections I intend to apply later this morning. Ian.

...; #reg " : 0x%08X\n", \ > + amdgpu_mm_rreg(adev, (reg), false)) > #define WREG32(reg, v) amdgpu_mm_wreg(adev, (reg), (v), false) > #define WREG32_IDX(reg, v) amdgpu_mm_wreg(adev, (reg), (v), true) > #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c > index 857ba0897159..3889486f71fe 100644 > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.c > @@ -74,9 +74,9 @@ static void amdgpu_afmt_...

Hi all, First thing first: It works, I now no longer have a few dropped frames every 10s on my testbox here with the pageflip i-g-t tests. Random notes: - New design has per-crtc locks to protect the crtc input-side (pageflip, cursor) for r/w and the output state of the crtc (mode, dpms) as read-only. It also required completely revamped fb lifecycle management, those are now refcounted

First off, Apologies for the massive patch series... This series boots a 32-bit dom0 kernel to a command prompt on an ARMv8 (AArch64) model. The kernel is the same one as I am currently using with the 32 bit hypervisor I haven''t yet tried starting a guest or anything super advanced like that ;-). Also there is not real support for 64-bit domains at all, although in one or two places I