Displaying 20 results from an estimated 39 matches for "_bits".
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2004 Aug 06
0
Multiple Frames per Packet
Hi, I'm using Speex and I want to pack multiple frames into a single
packet. The manual (section 4.5) says to call "speex_encode()"
multiple times before calling "speex_bits_write()", and then call
"speex_decode()" until it returns -1. However, when I try that
"speex_decode()" never returns -1, and it enters an infinite loop.
I'm using 1.0.4.
Any suggestions? Surely this isn't a new question. (Incidentally,
the Xiph.org archives of...
2011 Mar 03
0
[PATCH] Eliminate the ec_int32 and ec_uint32 typedefs.
...X, c
void quant_all_bands(int encode, const CELTMode *m, int start, int end,
celt_norm *_X, celt_norm *_Y, unsigned char *collapse_masks, const celt_ener *bandE, int *pulses,
int shortBlocks, int spread, int dual_stereo, int intensity, int *tf_res, int resynth,
- celt_int32 total_bits, celt_int32 balance, ec_ctx *ec, int LM, int codedBands, ec_uint32 *seed)
+ celt_int32 total_bits, celt_int32 balance, ec_ctx *ec, int LM, int codedBands, celt_uint32 *seed)
{
int i;
celt_int32 remaining_bits;
diff --git a/libcelt/bands.h b/libcelt/bands.h
index d0fcf1b..d3d3dc8 10064...
2020 Jul 16
0
[PATCH vhost next 08/10] vdpa/mlx5: Add support library for mlx5 VDPA implementation
...lx5/driver.h:52,
from drivers/vdpa/mlx5/core/resources.c:4:
drivers/vdpa/mlx5/core/resources.c: In function 'create_uctx':
>> include/linux/mlx5/device.h:65:36: error: invalid application of 'sizeof' to incomplete type 'struct mlx5_ifc_create_uctx_out_bits'
65 | #define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
| ^~~~~~
drivers/vdpa/mlx5/core/resources.c:52:10: note: in expansion of macro 'MLX5_ST_SZ_DW'
52 | u32 out[MLX5_ST_SZ_DW(create_uctx_out)] = {};...
2020 Aug 05
0
[PATCH V4 linux-next 00/12] VDPA support for Mellanox ConnectX devices
...from ./include/linux/list.h:9,
from ./include/linux/module.h:12,
from drivers/vdpa/mlx5/net/main.c:4:
drivers/vdpa/mlx5/net/main.c: In function ?required_caps_supported?:
././include/linux/compiler_types.h:129:35: error: ?struct mlx5_ifc_device_virtio_emulation_cap_bits? has no member named ?event_mode?
129 | #define __compiler_offsetof(a, b) __builtin_offsetof(a, b)
| ^~~~~~~~~~~~~~~~~~
./include/uapi/linux/swab.h:115:54: note: in definition of macro ?__swab32?
115 | #define __swab32(x) (__u32)__builtin_bswap32((__u32)(...
2020 Aug 05
0
[PATCH V4 linux-next 00/12] VDPA support for Mellanox ConnectX devices
...; from ./include/linux/module.h:12,
> > from drivers/vdpa/mlx5/net/main.c:4:
> > drivers/vdpa/mlx5/net/main.c: In function ?required_caps_supported?:
> > ././include/linux/compiler_types.h:129:35: error: ?struct mlx5_ifc_device_virtio_emulation_cap_bits? has no member named ?event_mode?
> > 129 | #define __compiler_offsetof(a, b) __builtin_offsetof(a, b)
> > | ^~~~~~~~~~~~~~~~~~
> > ./include/uapi/linux/swab.h:115:54: note: in definition of macro ?__swab32?
> > 115 | #define __swa...
2020 Jul 16
0
[PATCH vhost next 10/10] vdpa/mlx5: Add VDPA driver for supported mlx5 devices
...| ^~~~~~~~~~~~~~
drivers/vdpa/mlx5/net/mlx5_vnet.c:1192:2: note: in expansion of macro 'MLX5_SET'
1192 | MLX5_SET(rqtc, rqtc, list_q_type, MLX5_RQTC_LIST_Q_TYPE_VIRTIO_NET_Q);
| ^~~~~~~~
include/linux/compiler_types.h:135:35: error: 'struct mlx5_ifc_rqtc_bits' has no member named 'list_q_type'
135 | #define __compiler_offsetof(a, b) __builtin_offsetof(a, b)
| ^~~~~~~~~~~~~~~~~~
include/uapi/linux/swab.h:115:54: note: in definition of macro '__swab32'
115 | #define __swab32(x) (_...
2007 Oct 10
0
encode return 0
...plingRate = &_SamplingRate)
{
speex_encoder_ctl(_State, 3 /*SPEEX_GET_FRAME_SIZE*/, __FrameSize);
speex_encoder_ctl(_State, 16 /*SPEEX_SET_COMPLEXITY*/,
__Complexity);
speex_encoder_ctl(_State, 24 /*SPEEX_SET_SAMPLING_RATE*/,
__SamplingRate);
}
_Bits = new SpeexBits();
//Data encoding
public byte[] ProcessData(byte[] ABuffer, int ADataSize)
{
int OutputDataSize;
short[] TempData = new short[ADataSize];
for (int Index = ADataSize-1; Index >= 0; Index--)
TempData[Index] = (short)((ABuffer[Index] <...
2020 Jul 16
0
[PATCH vhost next 09/10] vdpa/mlx5: Add shared memory registration code
...fld)) \
| ^~~~~~~~~~~~~~
drivers/vdpa/mlx5/core/mr.c:194:2: note: in expansion of macro 'MLX5_SET'
194 | MLX5_SET(create_mkey_in, in, uid, mvdev->res.uid);
| ^~~~~~~~
include/linux/compiler_types.h:135:35: error: 'struct mlx5_ifc_create_mkey_in_bits' has no member named 'uid'
135 | #define __compiler_offsetof(a, b) __builtin_offsetof(a, b)
| ^~~~~~~~~~~~~~~~~~
include/uapi/linux/swab.h:115:54: note: in definition of macro '__swab32'
115 | #define __swab32(x) (__u32)__b...
2020 Jul 16
0
[PATCH vhost next 09/10] vdpa/mlx5: Add shared memory registration code
...17 | #define offsetof(TYPE, MEMBER) __compiler_offsetof(TYPE, MEMBER)
| ^~~~~~~~~~~~~~~~~~~
include/linux/mlx5/device.h:51:35: note: in expansion of macro 'offsetof'
51 | #define __mlx5_bit_off(typ, fld) (offsetof(struct mlx5_ifc_##typ##_bits, fld))
| ^~~~~~~~
include/linux/mlx5/device.h:56:70: note: in expansion of macro '__mlx5_bit_off'
56 | #define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
|...
2014 Jun 15
0
[PATCH 03/11] qspinlock: Add pending bit
...qspinlock_types.h
@@ -39,8 +39,9 @@ typedef struct qspinlock {
* Bitfields in the atomic value:
*
* 0- 7: locked byte
- * 8- 9: tail index
- * 10-31: tail cpu (+1)
+ * 8: pending
+ * 9-10: tail index
+ * 11-31: tail cpu (+1)
*/
#define _Q_SET_MASK(type) (((1U << _Q_ ## type ## _BITS) - 1)\
<< _Q_ ## type ## _OFFSET)
@@ -48,7 +49,11 @@ typedef struct qspinlock {
#define _Q_LOCKED_BITS 8
#define _Q_LOCKED_MASK _Q_SET_MASK(LOCKED)
-#define _Q_TAIL_IDX_OFFSET (_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)
+#define _Q_PENDING_OFFSET (_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)
+...
2014 Apr 17
0
[PATCH v9 03/19] qspinlock: Add pending bit
...qspinlock_types.h
@@ -39,8 +39,9 @@ typedef struct qspinlock {
* Bitfields in the atomic value:
*
* 0- 7: locked byte
- * 8- 9: tail index
- * 10-31: tail cpu (+1)
+ * 8: pending
+ * 9-10: tail index
+ * 11-31: tail cpu (+1)
*/
#define _Q_SET_MASK(type) (((1U << _Q_ ## type ## _BITS) - 1)\
<< _Q_ ## type ## _OFFSET)
@@ -48,7 +49,11 @@ typedef struct qspinlock {
#define _Q_LOCKED_BITS 8
#define _Q_LOCKED_MASK _Q_SET_MASK(LOCKED)
-#define _Q_TAIL_IDX_OFFSET (_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)
+#define _Q_PENDING_OFFSET (_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)
+...
2014 May 07
0
[PATCH v10 03/19] qspinlock: Add pending bit
...qspinlock_types.h
@@ -39,8 +39,9 @@ typedef struct qspinlock {
* Bitfields in the atomic value:
*
* 0- 7: locked byte
- * 8- 9: tail index
- * 10-31: tail cpu (+1)
+ * 8: pending
+ * 9-10: tail index
+ * 11-31: tail cpu (+1)
*/
#define _Q_SET_MASK(type) (((1U << _Q_ ## type ## _BITS) - 1)\
<< _Q_ ## type ## _OFFSET)
@@ -48,7 +49,11 @@ typedef struct qspinlock {
#define _Q_LOCKED_BITS 8
#define _Q_LOCKED_MASK _Q_SET_MASK(LOCKED)
-#define _Q_TAIL_IDX_OFFSET (_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)
+#define _Q_PENDING_OFFSET (_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)
+...
2015 Mar 16
0
[PATCH 3/9] qspinlock: Add pending bit
...qspinlock_types.h
@@ -36,8 +36,9 @@ typedef struct qspinlock {
* Bitfields in the atomic value:
*
* 0- 7: locked byte
- * 8- 9: tail index
- * 10-31: tail cpu (+1)
+ * 8: pending
+ * 9-10: tail index
+ * 11-31: tail cpu (+1)
*/
#define _Q_SET_MASK(type) (((1U << _Q_ ## type ## _BITS) - 1)\
<< _Q_ ## type ## _OFFSET)
@@ -45,7 +46,11 @@ typedef struct qspinlock {
#define _Q_LOCKED_BITS 8
#define _Q_LOCKED_MASK _Q_SET_MASK(LOCKED)
-#define _Q_TAIL_IDX_OFFSET (_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)
+#define _Q_PENDING_OFFSET (_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)
+...
2014 Jun 15
0
[PATCH 01/11] qspinlock: A simple generic 4-byte queue spinlock
...linux/atomic.h>
+#include <linux/bug.h>
+#endif
+
+typedef struct qspinlock {
+ atomic_t val;
+} arch_spinlock_t;
+
+/*
+ * Bitfields in the atomic value:
+ *
+ * 0- 7: locked byte
+ * 8- 9: tail index
+ * 10-31: tail cpu (+1)
+ */
+#define _Q_SET_MASK(type) (((1U << _Q_ ## type ## _BITS) - 1)\
+ << _Q_ ## type ## _OFFSET)
+#define _Q_LOCKED_OFFSET 0
+#define _Q_LOCKED_BITS 8
+#define _Q_LOCKED_MASK _Q_SET_MASK(LOCKED)
+
+#define _Q_TAIL_IDX_OFFSET (_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)
+#define _Q_TAIL_IDX_BITS 2
+#define _Q_TAIL_IDX_MASK _Q_SET_MASK(TAIL_IDX)
+
+#de...
2014 Jun 17
5
[PATCH 03/11] qspinlock: Add pending bit
...qspinlock {
> * Bitfields in the atomic value:
> *
> * 0- 7: locked byte
> - * 8- 9: tail index
> - * 10-31: tail cpu (+1)
> + * 8: pending
> + * 9-10: tail index
> + * 11-31: tail cpu (+1)
> */
> #define _Q_SET_MASK(type) (((1U << _Q_ ## type ## _BITS) - 1)\
> << _Q_ ## type ## _OFFSET)
> @@ -48,7 +49,11 @@ typedef struct qspinlock {
> #define _Q_LOCKED_BITS 8
> #define _Q_LOCKED_MASK _Q_SET_MASK(LOCKED)
>
> -#define _Q_TAIL_IDX_OFFSET (_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)
> +#define _Q_PENDING_OFFSET (_...
2014 Jun 17
5
[PATCH 03/11] qspinlock: Add pending bit
...qspinlock {
> * Bitfields in the atomic value:
> *
> * 0- 7: locked byte
> - * 8- 9: tail index
> - * 10-31: tail cpu (+1)
> + * 8: pending
> + * 9-10: tail index
> + * 11-31: tail cpu (+1)
> */
> #define _Q_SET_MASK(type) (((1U << _Q_ ## type ## _BITS) - 1)\
> << _Q_ ## type ## _OFFSET)
> @@ -48,7 +49,11 @@ typedef struct qspinlock {
> #define _Q_LOCKED_BITS 8
> #define _Q_LOCKED_MASK _Q_SET_MASK(LOCKED)
>
> -#define _Q_TAIL_IDX_OFFSET (_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)
> +#define _Q_PENDING_OFFSET (_...
2015 Mar 16
0
[PATCH 1/9] qspinlock: A simple generic 4-byte queue spinlock
...nux/types.h>
+#include <linux/atomic.h>
+#endif
+
+typedef struct qspinlock {
+ atomic_t val;
+} arch_spinlock_t;
+
+/*
+ * Bitfields in the atomic value:
+ *
+ * 0- 7: locked byte
+ * 8- 9: tail index
+ * 10-31: tail cpu (+1)
+ */
+#define _Q_SET_MASK(type) (((1U << _Q_ ## type ## _BITS) - 1)\
+ << _Q_ ## type ## _OFFSET)
+#define _Q_LOCKED_OFFSET 0
+#define _Q_LOCKED_BITS 8
+#define _Q_LOCKED_MASK _Q_SET_MASK(LOCKED)
+
+#define _Q_TAIL_IDX_OFFSET (_Q_LOCKED_OFFSET + _Q_LOCKED_BITS)
+#define _Q_TAIL_IDX_BITS 2
+#define _Q_TAIL_IDX_MASK _Q_SET_MASK(TAIL_IDX)
+
+#de...
2014 Jun 15
28
[PATCH 00/11] qspinlock with paravirt support
Since Waiman seems incapable of doing simple things; here's my take on the
paravirt crap.
The first few patches are taken from Waiman's latest series, but the virt
support is completely new. Its primary aim is to not mess up the native code.
I've not stress tested it, but the virt and paravirt (kvm) cases boot on simple
smp guests. I've not done Xen, but the patch should be
2014 Jun 15
28
[PATCH 00/11] qspinlock with paravirt support
Since Waiman seems incapable of doing simple things; here's my take on the
paravirt crap.
The first few patches are taken from Waiman's latest series, but the virt
support is completely new. Its primary aim is to not mess up the native code.
I've not stress tested it, but the virt and paravirt (kvm) cases boot on simple
smp guests. I've not done Xen, but the patch should be
2014 Oct 16
15
[PATCH v12 00/11] qspinlock: a 4-byte queue spinlock with PV support
v11->v12:
- Based on PeterZ's version of the qspinlock patch
(https://lkml.org/lkml/2014/6/15/63).
- Incorporated many of the review comments from Konrad Wilk and
Paolo Bonzini.
- The pvqspinlock code is largely from my previous version with
PeterZ's way of going from queue tail to head and his idea of
using callee saved calls to KVM and XEN codes.
v10->v11:
- Use a