Displaying 8 results from an estimated 8 matches for "64byte".
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2010 Apr 28
1
[LLVMdev] Setting alignment for a ByVal argument
I could not get the same .bc file work with llvm 2.7 on x86_64 either.
This is the address I got for a byval argument meant to be aligned to
64byte boundary.
0x7fff3f0ae030
Any more pointers?
Arushi
PS: Is the IR representation in 2.7 any different, that I should not
use the same bitcode file.
On Tue, Apr 27, 2010 at 3:22 PM, Duncan Sands <baldrick at free.fr> wrote:
> Hi Arushi,
>
>> Thanks for the help. I tried this...
2009 Jul 06
1
lvb length issue [was Re: [ocfs2-tools-devel] question of ocfs2_controld (Jun 27)]
...evel/2009-June/001891.html
Joel Becker Wrote:
> On Sat, Jun 27, 2009 at 03:46:04AM +0800, Coly Li wrote:
>> Joel Becker Wrote:
>>> On Sat, Jun 27, 2009 at 03:00:05AM +0800, Coly Li wrote:
>> [snip]
>>>> My original purpose is to find where to initiate a lvb with 64bytes, but from
>>>> mount.ocfs2 code, I don't find anywhere to create a dlm lockspace (before create
>>>> a lock) so far.
>>> I'm not sure why you need an LVB in mount.ocfs2, let alone a dlm
>>> lockspace.
>>>
>> Hi Joel,
>>
>&g...
2010 Apr 27
0
[LLVMdev] Setting alignment for a ByVal argument
Hi Arushi,
> Thanks for the help. I tried this out, but on x86_64 and with llvm 2.6
> and llvm-gcc 4.2.1, I dont seem to get an aligned variable.
does it work with llvm-2.7 (just released)?
Ciao,
Duncan.
2010 Apr 27
2
[LLVMdev] Setting alignment for a ByVal argument
Hi,
Thanks for the help. I tried this out, but on x86_64 and with llvm 2.6
and llvm-gcc 4.2.1, I dont seem to get an aligned variable.
This is the function definition that I have
define internal fastcc void @walksub(%struct.hgstruct* noalias
nocapture sret %agg.result, %struct.node* %p, double %dsq,
%struct.hgstruct* byval align 64 %hg, i32 %level) nounwind {
And these are the call sites,
2009 Jul 29
9
Quagga on Xen - Latency / Bandwidth?
I was wondering if anyone is running Quagga on Xen? What is
throughput/latency like?
Was looking for about a gig of mixed packet size BGP throughput.
Hardware is Opteron 4 Way Quad cores, was thinking paravirt with a
couple of dedicated cores and maybe the addition of Solarflare 10GB
Direct IO NICs might give the required performance level but I am
unsure. The other option is multi-queue Intel
2006 Jan 09
15
MTU and Voice Delay (latency??)
Our users are experiencing some unacceptable delay when trying to have a
conversation. The delay is so noticeable that they keep stepping on each
others words and resort to calling the customers via cell phone.
Here is the setup
SDSL Connection (PPPoA)
Speedtouch 610 SDSL Modem
3Com 2224PWR Plus Switch (phones on separate VLAN)
8 Cisco 796 Phones
All connecting to a remote Asterisk Server.
We
2016 Nov 27
4
[RFC] Supporting ARM's SVE in LLVM
I'm sorry.. may I interrupt for a minute and try to grok things for a
bit different angle..
While the VL can vary.. in practice wouldn't the cost of vectorization
and width be tied more to the hardware implementation than anything
else? The cost of vectorizing thread 1 vs 2 isn't likely to change?
(Am I drunk and mistaken?)
If the above holds true then the the length would be only
2010 Aug 06
4
nv vpe video decoder
Hello,
I have my work on the nv vpe video decoder in a functional
state. In case you didn't know this decoder accelerates mpeg2
video at the idct/mc level. I have verified that it works on
nv40 hardware. I believe it works on nv30 hardware (and
maybe some earlier hardware), but I cannot verify since I have
none.
I will reply with patches against the kernel, drm, ddx
and mesa for