Displaying 3 results from an estimated 3 matches for "5056r".
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1056r
2014 Aug 22
2
[LLVMdev] Help with definition of subregisters; spill, rematerialization and implicit uses
..., Quentin Colombet wrote:
[...]
> It seems that you will have to debug further the *** Bad machine code: Instruction loads from dead spill slot *** before we can be of any help.
Yes, I've done some more digging. Sorry for the long mail...
I get:
Inline spilling aN40_0_7:%vreg1954 [5000r,5056r:0)[5056r,5348r:1)
0 at 5000r 1 at 5056r
At this point I have the following live ranges for vreg1954:
%vreg1954 [5000r,5056r:0)[5056r,5348r:1) 0 at 5000r 1 at 5056r
And vreg1954 is mentioned in these instructions:
5000B %vreg1954:hi16<def,read-undef> = mv_any16 32766
[...]
5048B...
2014 Aug 19
2
[LLVMdev] Help with definition of subregisters; spill, rematerialization and implicit uses
Hi Quentin,
On 08/15/14 19:01, Quentin Colombet wrote:
[...]
>> The question is: How should true subregister definitions be
>> expressed so that they do not interfere with each other? See the
>> detailed problem description below.
>
> We do have a limitation in our current liveness tracking for
> sub-register. Therefore, I am not sure that is possible.
>
>
2014 Aug 15
2
[LLVMdev] Help with definition of subregisters; spill, rematerialization and implicit uses
...cided Reg5
can be rematerialized:
"Value Reg5:0 at 5000r may remat from Reg5:hi16<def,read-undef> = mv_any16
32766"
So it says Reg5 can be rematerialized by setting it's high part...
We also get:
reload: 5052r Reg5<def> = Load40FI <fi#2>
rewrite: 5056r Reg5:lo16<def> = mv_nimm6_ar16 0
So it inserts a reload of the full Reg5 prior to the setting of
Reg5:lo16, because it thinks there is an implicit use of Reg5 when
writing the low part??? This seems very weird to me.
The decision is based on the fact that MachineOperand::readsReg()
retur...