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...phi-join +[448B,496r:1) BB#1:# derived from  464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47 register: %vreg5 +[464r,592B:0) +[880B,992r:0) 480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48 register: %vreg6 +[480r,592B:0) +[592B,704r:0) +[880B,1056r:0) 496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49 register: %vreg7 +[496r,592B:0) +[880B,1088r:0) 512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7 register: %vreg29 +[512r,5...

...> BB#1:# derived from  > 464B%vreg5<def> = COPY %vreg47<kill>; R600_Reg32:%vreg5,%vreg47 > register: %vreg5 +[464r,592B:0) +[880B,992r:0) > 480B%vreg6<def> = COPY %vreg48<kill>; R600_Reg128:%vreg6,%vreg48 > register: %vreg6 +[480r,592B:0) +[592B,704r:0) +[880B,1056r:0) > 496B%vreg7<def> = COPY %vreg49<kill>; R600_Reg32:%vreg7,%vreg49 > register: %vreg7 +[496r,592B:0) +[880B,1088r:0) > 512B%vreg29<def> = SETGT_INT 0, 0, 1, 0, 0, 0, %vreg0, 0, 0, 0, %vreg7, 0, > 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg29,%vreg0,%vreg7 >...

Hi Vincent, On 24/10/2012 23:26, Vincent Lejeune wrote: > Hi, > > I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. > > The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : > > // BEFORE LOOP >

Hi, I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below. The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is : // BEFORE LOOP ... Some COPYs.... 400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2