search for: 3gib

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2015 Jul 08
2
CUDA fixed VA allocations and sparse mappings
...ever get a CPU > > address that low. But having a set of addresses reserved would be much > > better of course. > I'm thinking more about the top of the address space. As I understand > it, the kernel already splits the CPU virtual address space into > user/system areas (3GiB/1GiB for 32-bit IIUC), or something very > similar to that. > > Perhaps, if we can get at that information, we can use those same > definitions for GPU address space? Ah, I get what you're saying. Sure, I think that might be okay. Not sure how we would get at that information, t...
2015 Jul 08
2
CUDA fixed VA allocations and sparse mappings
On Wed, Jul 08, 2015 at 10:18:36AM +1000, Ben Skeggs wrote: > > There's some minimal state that needs to be mapped into GPU address space. > > One thing that comes to mind are pushbuffers, which are needed to submit > > stuff to any engine. > I guess you can probably use the start of the kernel's address space > carveout for these kind of mappings actually?
2015 Jul 08
2
CUDA fixed VA allocations and sparse mappings
...at low. But having a set of addresses reserved would be much > >> > better of course. > >> I'm thinking more about the top of the address space. As I understand > >> it, the kernel already splits the CPU virtual address space into > >> user/system areas (3GiB/1GiB for 32-bit IIUC), or something very > >> similar to that. > >> > >> Perhaps, if we can get at that information, we can use those same > >> definitions for GPU address space? > > > > Ah, I get what you're saying. Sure, I think that might be o...
2012 Feb 24
43
[Bug 46557] New: nouveau: nv40 display corruption in framebuffer and X lockups unless nouveau.noaccel=1
https://bugs.freedesktop.org/show_bug.cgi?id=46557 Bug #: 46557 Summary: nouveau: nv40 display corruption in framebuffer and X lockups unless nouveau.noaccel=1 Classification: Unclassified Product: xorg Version: git Platform: x86-64 (AMD64) OS/Version: Linux (All) Status: NEW Severity: