Displaying 6 results from an estimated 6 matches for "2x32".
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2018 Dec 20
2
RegBankSelect complex value mappings
...le:
/// E.g.,
/// Let say we have a 32-bit add and a <2 x 32-bit> vadd. We
/// can expand the
/// <2 x 32-bit> add into 2 x 32-bit add.
///
/// Currently the TableGen-like file would look like:
/// \code
/// PartialMapping[] = {
/// /*32-bit add*/ {0, 32, GPR},
/// /*2x32-bit add*/ {0, 32, GPR}, {0, 32, GPR}, // <-- Same entry 3x
/// /*<2x32-bit> vadd {0, 64, VPR}
/// }; // PartialMapping duplicated.
///
/// ValueMapping[] {
/// /*plain 32-bit add*/ {&PartialMapping[0], 1},
/// /*expanded vadd on 2xadd*/ {&PartialMapping[1], 2},
//...
2010 Feb 22
0
[LLVMdev] Paired register allocation problem
...does the same for 64-bit args in two 32-bit
registers, but always uses (Rn, Rn+1) pairs and is incapable of
scheduling the two 32-bit move instructions independently, since the
two are output at the very last minute by the last part of the
machine-dependent backend/
This is slow when moving such a 2x32-bit value to a 64-bit register in
one the ARM FPUs, since two 32-bit moves to the low and high halves
of the same FPU register incur a 7-cycle delay - a fairly common
occurrence when double args are moved into FPU regs for processing. If
it could schedule the two 32-bit moves separately, up to 6 ot...
2013 Apr 15
0
[LLVMdev] 64-bit add using 2 32-bit operations, guarantee of stuck together?
Using bundles here looks like a fragile way to handle that, IMHO.
Really, using a pseudo instruction seems the best approach for you.
For instance, you can match your add64 during isel with your pseudo instruction and expand it just before emitting the assembly file (add a pass using the hook: addPreEmitPass on your target).
-Quentin
On Apr 15, 2013, at 2:37 PM, Francois Pichet <pichet2000
2010 Feb 22
5
[LLVMdev] Paired register allocation problem
Hi Anton,
Thanks for reply
> I have defined registers, aliases and subregister set.
> > The problem is that register allocator is using 32bit registers that are
> > already used in a pair, for example:
> > lw $r0, 16[$r12] // load word to r0
> > ld $p0, 36[$r12] // load doubleword to p0
> > shl $p0, $p0, $r0 // shift left p0 by r0 and store result in p0
2013 Apr 15
2
[LLVMdev] 64-bit add using 2 32-bit operations, guarantee of stuck together?
I really have to force them to stuck together otherwise the carry will just
not work.
How about wrapping the 2 instructions in a bundle?
Would that be a way?
http://llvm.org/docs/CodeGenerator.html#machineinstr-bundles
On Mon, Apr 15, 2013 at 5:24 PM, Quentin Colombet <qcolombet at apple.com>wrote:
> Hi Francois,
>
> If you model the effect of your carry on the instructions, the
2015 Apr 03
2
[LLVMdev] How to enable use of 64bit load/store for 32bit architecture
> On Apr 2, 2015, at 2:07 PM, Tom Stellard <tom at stellard.net> wrote:
>
> On Thu, Apr 02, 2015 at 01:35:55PM -0700, Pete Cooper wrote:
>> Hi James, Jim
>>
>> If you *really* want this to work in selection DAG then there is a solution, but its not pretty.
>>
>> First make i64 not be legal. Then, assuming the regclass you gave has some subregs, you