Displaying 20 results from an estimated 20 matches for "192r".
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2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...60r:1) RESULT: [144r,160r:1)[160r,224r:0) 0 at 160r 1 at 144r
176B%vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21
register: %vreg24 +[176r,256r:0)
192B%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24 R600_Reg32:%vreg2
register: %vreg24 replace range with [176r,192r:1) RESULT: [176r,192r:1)[192r,256r:0) 0 at 192r 1 at 176r
208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
register: %vreg25 +[208r,272r:0)
224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23
register: %vreg26 +[224r,336r:0)
240B%vreg26:sel_z<def> = COPY %vr...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...1)[160r,224r:0) 0 at 160r 1 at 144r
> 176B%vreg24<def> = COPY %vreg21<kill>; R600_Reg128:%vreg24,%vreg21
> register: %vreg24 +[176r,256r:0)
> 192B%vreg24:sel_y<def> = COPY %vreg2; R600_Reg128:%vreg24
> R600_Reg32:%vreg2
> register: %vreg24 replace range with [176r,192r:1) RESULT:
> [176r,192r:1)[192r,256r:0) 0 at 192r 1 at 176r
> 208B%vreg25<def> = COPY %C1_Z; R600_Reg32:%vreg25
> register: %vreg25 +[208r,272r:0)
> 224B%vreg26<def> = COPY %vreg23<kill>; R600_Reg128:%vreg26,%vreg23
> register: %vreg26 +[224r,336r:0)
> 240B%vre...
2017 Sep 26
2
[MachineCopyPropagation] Issue with register forwarding/allocation/verifier in out-of-tree target
...ilure in his out-of-tree target
with the MachineCopyPropagation changes to forward registers (which is
currently reverted). The verification in question is:
*** Bad machine code: Multiple connected components in live interval ***
- function: utils_la_suite_matmul_ref
- interval: %vreg77
[192r,208B:0)[208B,260r:1)[312r,364r:2)[380r,464B:3) 0 at 192r 1 at 208B-phi
2 at 312r 3 at 380r
0: valnos 0 1 3
1: valnos 2
In this particular case, I believe that it is the greedy allocator that
is creating the multiple components in the %vreg77 live interval. If
you look at the attached debug du...
2017 Sep 26
0
[MachineCopyPropagation] Issue with register forwarding/allocation/verifier in out-of-tree target
...of-tree target with the MachineCopyPropagation changes to forward registers (which is currently reverted). The verification in question is:
>
> *** Bad machine code: Multiple connected components in live interval ***
> - function: utils_la_suite_matmul_ref
> - interval: %vreg77 [192r,208B:0)[208B,260r:1)[312r,364r:2)[380r,464B:3) 0 at 192r 1 at 208B-phi 2 at 312r 3 at 380r
> 0: valnos 0 1 3
> 1: valnos 2
>
> In this particular case, I believe that it is the greedy allocator that is creating the multiple components in the %vreg77 live interval. If you look at the...
2017 Sep 26
2
[MachineCopyPropagation] Issue with register forwarding/allocation/verifier in out-of-tree target
...with the MachineCopyPropagation changes to forward registers (which is currently reverted). The verification in question is:
>>
>> *** Bad machine code: Multiple connected components in live interval ***
>> - function: utils_la_suite_matmul_ref
>> - interval: %vreg77 [192r,208B:0)[208B,260r:1)[312r,364r:2)[380r,464B:3) 0 at 192r 1 at 208B-phi 2 at 312r 3 at 380r
>> 0: valnos 0 1 3
>> 1: valnos 2
>>
>> In this particular case, I believe that it is the greedy allocator that is creating the multiple components in the %vreg77 live interval. If y...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 24/10/2012 23:26, Vincent Lejeune wrote:
> Hi,
>
> I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
>
2017 Sep 26
0
[MachineCopyPropagation] Issue with register forwarding/allocation/verifier in out-of-tree target
...opyPropagation changes to forward registers (which is currently reverted). The verification in question is:
>>>
>>> *** Bad machine code: Multiple connected components in live interval ***
>>> - function: utils_la_suite_matmul_ref
>>> - interval: %vreg77 [192r,208B:0)[208B,260r:1)[312r,364r:2)[380r,464B:3) 0 at 192r 1 at 208B-phi 2 at 312r 3 at 380r
>>> 0: valnos 0 1 3
>>> 1: valnos 2
>>>
>>> In this particular case, I believe that it is the greedy allocator that is creating the multiple components in the %vreg77 liv...
2017 Sep 27
2
[MachineCopyPropagation] Issue with register forwarding/allocation/verifier in out-of-tree target
...t;>> (which is currently reverted). The verification in question is:
>>>>
>>>> *** Bad machine code: Multiple connected components in live interval ***
>>>> - function: utils_la_suite_matmul_ref
>>>> - interval: %vreg77
>>>> [192r,208B:0)[208B,260r:1)[312r,364r:2)[380r,464B:3) 0 at 192r
>>>> 1 at 208B-phi 2 at 312r 3 at 380r
>>>> 0: valnos 0 1 3
>>>> 1: valnos 2
>>>>
>>>> In this particular case, I believe that it is the greedy allocator
>>>> that is...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
..., %vreg2, 1, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg7 R600_TReg32:%vreg2
register: %vreg7 +[128r,144r:0)
144B%vreg8<def> = ADD 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg5<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg8,%vreg7,%vreg5
register: %vreg8 +[144r,192r:0)
160B%vreg9:sel_x<def,read-undef> = COPY %vreg6<kill>; R600_Reg128:%vreg9 R600_Reg32:%vreg6
register: %vreg9 +[160r,176r:0)
176B%vreg11<def> = COPY %vreg9<kill>; R600_Reg128:%vreg11,%vreg9
register: %vreg11 +[176r,208r:0)
192B%vreg11:sel_y<def> = COPY %vreg8<kill&...
2017 Sep 27
0
[MachineCopyPropagation] Issue with register forwarding/allocation/verifier in out-of-tree target
...d registers (which is currently reverted). The verification in question is:
>>>>>
>>>>> *** Bad machine code: Multiple connected components in live interval ***
>>>>> - function: utils_la_suite_matmul_ref
>>>>> - interval: %vreg77 [192r,208B:0)[208B,260r:1)[312r,364r:2)[380r,464B:3) 0 at 192r 1 at 208B-phi 2 at 312r 3 at 380r
>>>>> 0: valnos 0 1 3
>>>>> 1: valnos 2
>>>>>
>>>>> In this particular case, I believe that it is the greedy allocator that is creating the multip...
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi,
I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...lob/master/lib/source/ecc_dh.c#L139
Thanks,
Prathamesh
-------------- next part --------------
PreferIndirect: 1
PreferIndirect: 1
PreferIndirect: 1
Computing live-in reg-units in ABI blocks.
0B %bb.0 R0#0 R1#0 R2#0
Created 3 new intervals.
********** INTERVALS **********
R0 [0B,48r:0)[96r,144r:3)[192r,240r:2)[288r,336r:1) 0 at 0B-phi 1 at 288r 2 at 192r 3 at 96r
R1 [0B,32r:0)[112r,144r:3)[208r,240r:2)[304r,336r:1) 0 at 0B-phi 1 at 304r 2 at 208r 3 at 112r
R2 [0B,16r:0)[128r,144r:3)[224r,240r:2)[320r,336r:1) 0 at 0B-phi 1 at 320r 2 at 224r 3 at 128r
%0 [48r,288r:0) 0 at 48r weight:0.000000e+0...
2018 Sep 11
2
linear-scan RA
...1 = COPY %0
> JMP_1 %bb.3
>
> bb.3:
> NOOP implicit %1
>
>
>
> $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
> ********** INTERVALS **********
> %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
> %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi weight:0.000000e+00
> RegMasks:
> ********** MACHINEINSTRS **********
> # Machine code for function somefunc: NoPHIs
>
> 0B bb.0:
> successors: %bb.2(0x80000000); %bb.2(100.00%)
>
> 16B %0:gr32 = MOV32ri 42
> 32B JB_1 %bb.2, i...
2018 Sep 11
2
linear-scan RA
...; > bb.3:
> > NOOP implicit %1
> >
> >
> >
> > $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
> > ********** INTERVALS **********
> > %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
> > %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi
> weight:0.000000e+00
> > RegMasks:
> > ********** MACHINEINSTRS **********
> > # Machine code for function somefunc: NoPHIs
> >
> > 0B bb.0:
> > successors: %bb.2(0x80000000); %bb.2(100.00%)
> >
> > 16B %0:gr...
2018 Sep 11
2
linear-scan RA
The phi instruction is irrelevant; just the way I think about things.
The question is if the allocator believes that t0 and t2 interfere.
Perhaps the coalescing example was too simple.
In the general case, we can't coalesce without a notion of interference.
My worry is that looking at interference by ranges of instruction numbers
leads to inaccuracies when a range is introduced by a copy.
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...list
> > llvm-dev at lists.llvm.org
> > https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
-------------- next part --------------
Computing live-in reg-units in ABI blocks.
0B %bb.0 R0#0 R1#0 R2#0
Created 3 new intervals.
********** INTERVALS **********
R0 [0B,48r:0)[96r,144r:4)[192r,240r:3)[288r,336r:2)[384r,432r:1) 0 at 0B-phi 1 at 384r 2 at 288r 3 at 192r 4 at 96r
R1 [0B,32r:0)[112r,144r:4)[208r,240r:3)[304r,336r:2)[400r,432r:1) 0 at 0B-phi 1 at 400r 2 at 304r 3 at 208r 4 at 112r
R2 [0B,16r:0)[128r,144r:4)[224r,240r:3)[320r,336r:2)[416r,432r:1) 0 at 0B-phi 1 at 416r 2 at...
2018 Sep 11
2
linear-scan RA
...;
> >> >
> >> >
> >> > $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
> >> > ********** INTERVALS **********
> >> > %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
> >> > %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi
> weight:0.000000e+00
> >> > RegMasks:
> >> > ********** MACHINEINSTRS **********
> >> > # Machine code for function somefunc: NoPHIs
> >> >
> >> > 0B bb.0:
> >> > successors: %bb.2(0x80...
2018 Sep 11
2
linear-scan RA
...t;>>>
>>>>>> $ llc -run-pass=liveintervals -debug-only=regalloc test.mir
>>>>>> ********** INTERVALS **********
>>>>>> %0 [16r,64B:0)[112B,144r:0) 0 at 16r weight:0.000000e+00
>>>>>> %1 [80r,112B:1)[144r,176B:0)[176B,192r:2) 0 at 144r 1 at 80r 2 at 176B-phi weight:0.000000e+00
>>>>>> RegMasks:
>>>>>> ********** MACHINEINSTRS **********
>>>>>> # Machine code for function somefunc: NoPHIs
>>>>>>
>>>>>> 0B bb.0:
>>>>...
2013 Mar 19
0
[LLVMdev] setCC and brcond
...t;, 0; mem:LD4[%retval] GPRegs:%vreg4
register: %vreg4 +[160r,176r:0)
176B %R2<def> = COPY %vreg4<kill>; GPRegs:%vreg4
192B RET %R2<imp-use,kill>
Computing live-in reg-units in ABI blocks.
0B BB#0 R2#0
Created 1 new intervals.
********** INTERVALS **********
R2 = [0B,16r:0)[176r,192r:1) 0 at 0B-phi 1 at 176r
%vreg0 = [16r,32r:0) 0 at 16r
%vreg2 = [112r,128r:0) 0 at 112r
%vreg3 = [64r,80r:0) 0 at 64r
%vreg4 = [160r,176r:0) 0 at 160r
RegMasks:
********** MACHINEINSTRS **********
# Machine code for function isZero: Post SSA
Frame Objects:
fi#0: size=4, align=4, at location...