Displaying 10 results from an estimated 10 matches for "128r".
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2012 Oct 25
2
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...%vreg16 +[32r,240r:0)
48B%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
register: %vreg15 +[48r,160r:0)
64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14
register: %vreg14 +[64r,96r:0)
80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
register: %vreg18 +[80r,128r:0)
96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>; R600_Reg128:%vreg19 R600_TReg32:%vreg14
register: %vreg19 +[96r,144r:0)
112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
register: %vreg2 +[112r,400r:0)
128B%vreg21:sel_x<def,read-undef> = COPY %vreg18<kill>; R60...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
...%vreg15<def> = COPY %T1_Y<kill>; R600_TReg32:%vreg15
> register: %vreg15 +[48r,160r:0)
> 64B%vreg14<def> = COPY %T1_X<kill>; R600_TReg32:%vreg14
> register: %vreg14 +[64r,96r:0)
> 80B%vreg18<def> = COPY %C1_X; R600_Reg32:%vreg18
> register: %vreg18 +[80r,128r:0)
> 96B%vreg19:sel_x<def,read-undef> = COPY %vreg14<kill>;
> R600_Reg128:%vreg19 R600_TReg32:%vreg14
> register: %vreg19 +[96r,144r:0)
> 112B%vreg2<def> = COPY %C1_Y; R600_Reg32:%vreg2
> register: %vreg2 +[112r,400r:0)
> 128B%vreg21:sel_x<def,read-undef>...
2018 Apr 23
2
pre-RA scheduling/live register analysis optimization (handle move) forcing spill of registers
...ass:%vreg8
176B MOVSUTO_SU_os_rpc %SU_ROFF0<kill>, %RPC<imp-def,dead>
192B NOP
# End machine code for function addproddivConst.
handleMove 64B -> 104B: %vreg4<def> = COPY %vreg3; FPUaOffsetClass:%vreg4 FPUaROUTMULRegisterClass:%vreg3
%vreg4: [64r,128r:0) 0 at 64r
--> [104r,128r:0) 0 at 104r
%vreg3: [48r,64r:0) 0 at 48r
--> [48r,104r:0) 0 at 48r
# *** IR Dump After Machine Instruction Scheduler ***:
# Machine code for function addproddivConst: Post SSA
Function Live Ins: %FA_ROFF1 in %vreg0
0B BB#0:...
2012 Oct 25
0
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi Vincent,
On 24/10/2012 23:26, Vincent Lejeune wrote:
> Hi,
>
> I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
>
> The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
>
> // BEFORE LOOP
>
2012 Oct 24
3
[LLVMdev] RegisterCoalescing Pass seems to ignore part of CFG.
Hi,
I don't know if my llvm ir code is faulty, or if I spot a bug in the RegisterCoalescing Pass, so I'm posting my issue on the ML. Shader and print-before-all dump are given below.
The interessing part is the vreg6/vreg48 reduction : before RegCoalescing, the machine code is :
// BEFORE LOOP
... Some COPYs....
400B%vreg47<def> = COPY %vreg2<kill>; R600_Reg32:%vreg47,%vreg2
2020 Mar 31
2
[ARM] Register pressure with -mthumb forces register reload before each call
...in ABI blocks.
0B %bb.0 R0#0 R1#0 R2#0
Created 3 new intervals.
********** INTERVALS **********
R0 [0B,48r:0)[96r,144r:3)[192r,240r:2)[288r,336r:1) 0 at 0B-phi 1 at 288r 2 at 192r 3 at 96r
R1 [0B,32r:0)[112r,144r:3)[208r,240r:2)[304r,336r:1) 0 at 0B-phi 1 at 304r 2 at 208r 3 at 112r
R2 [0B,16r:0)[128r,144r:3)[224r,240r:2)[320r,336r:1) 0 at 0B-phi 1 at 320r 2 at 224r 3 at 128r
%0 [48r,288r:0) 0 at 48r weight:0.000000e+00
%1 [32r,304r:0) 0 at 32r weight:0.000000e+00
%2 [16r,320r:0) 0 at 16r weight:0.000000e+00
%3 [80r,336r:0) 0 at 80r weight:0.000000e+00
RegMasks: 144r 240r 336r
********** MA...
2020 Apr 07
2
[ARM] Register pressure with -mthumb forces register reload before each call
If I'm understanding what's going on in this test correctly, what's happening is:
* ARMTargetLowering::LowerCall prefers indirect calls when a function is called at least 3 times in minsize
* In thumb 1 (without -fno-omit-frame-pointer) we have effectively only 3 callee-saved registers (r4-r6)
* The function has three arguments, so those three plus the register we need to hold the
2020 Apr 15
4
[ARM] Register pressure with -mthumb forces register reload before each call
...3 new intervals.
********** INTERVALS **********
R0 [0B,48r:0)[96r,144r:4)[192r,240r:3)[288r,336r:2)[384r,432r:1) 0 at 0B-phi 1 at 384r 2 at 288r 3 at 192r 4 at 96r
R1 [0B,32r:0)[112r,144r:4)[208r,240r:3)[304r,336r:2)[400r,432r:1) 0 at 0B-phi 1 at 400r 2 at 304r 3 at 208r 4 at 112r
R2 [0B,16r:0)[128r,144r:4)[224r,240r:3)[320r,336r:2)[416r,432r:1) 0 at 0B-phi 1 at 416r 2 at 320r 3 at 224r 4 at 128r
%0 [48r,416r:0) 0 at 48r weight:0.000000e+00
%1 [32r,400r:0) 0 at 32r weight:0.000000e+00
%2 [16r,320r:0) 0 at 16r weight:0.000000e+00
%3 [80r,432r:0) 0 at 80r weight:0.000000e+00
RegMasks: 144r...
2013 Mar 19
0
[LLVMdev] setCC and brcond
...:%vreg0
BB#1: # derived from if.then
64B %vreg3<def> = MOVri 1; GPRegs:%vreg3
register: %vreg3 +[64r,80r:0)
80B STWi13 <fi#0>, 0, %vreg3<kill>; mem:ST4[%retval] GPRegs:%vreg3
BB#2: # derived from if.else
112B %vreg2<def> = MOVri 0; GPRegs:%vreg2
register: %vreg2 +[112r,128r:0)
128B STWi13 <fi#0>, 0, %vreg2<kill>; mem:ST4[%retval] GPRegs:%vreg2
BB#3: # derived from return
160B %vreg4<def> = LDWi13 <fi#0>, 0; mem:LD4[%retval] GPRegs:%vreg4
register: %vreg4 +[160r,176r:0)
176B %R2<def> = COPY %vreg4<kill>; GPRegs:%vreg4
192B RET %R2...
2012 Oct 20
2
[LLVMdev] RegisterCoalescing pass crashes with ImplicitDef registers
...= ADD 0, 0, 1, 0, 0, 0, %vreg4<kill>, 0, 0, 0, %vreg5, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg6,%vreg4,%vreg5
register: %vreg6 +[112r,160r:0)
128B%vreg7<def> = MOV 1, 0, 0, 0, %vreg2, 1, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg7 R600_TReg32:%vreg2
register: %vreg7 +[128r,144r:0)
144B%vreg8<def> = ADD 0, 0, 1, 0, 0, 0, %vreg7<kill>, 0, 0, 0, %vreg5<kill>, 0, 0, 0, 1, pred:%PRED_SEL_OFF, 0; R600_Reg32:%vreg8,%vreg7,%vreg5
register: %vreg8 +[144r,192r:0)
160B%vreg9:sel_x<def,read-undef> = COPY %vreg6<kill>; R600_Reg128:%vreg9 R600_Reg32:%...