search for: 0x0fffffff

...g and found this: Apr 9 17:49:29 phoenix kernel: [ 27.490852] architecture does not support 28bit PCI busmaster DMA Grepping the kernel I came up with this, from sound/pci/ice1712/ice1712.c: /* check, if we can restrict PCI DMA transfers to 28 bits */ if (pci_set_dma_mask(pci, 0x0fffffff) < 0 || pci_set_consistent_dma_mask(pci, 0x0fffffff) < 0) { snd_printk(KERN_ERR "architecture does not support 28bit PCI busmaster DMA\n"); pci_disable_device(pci); return -ENXIO; } I commented it out, and the modu...

...tools/libxc/xc_linux_save.c 2007-02-12 09:05:24.000000000 +0100 @@ -495,7 +495,7 @@ static int canonicalize_pagetable(unsign hstart = (hvirt_start >> L2_PAGETABLE_SHIFT_PAE) & 0x1ff; he = ((const uint64_t *) spage)[hstart]; - if ( ((he >> PAGE_SHIFT) & 0x0fffffff) == m2p_mfn0 ) { + if ( ((he >> PAGE_SHIFT) & MFN_MASK_X86) == m2p_mfn0 ) { /* hvirt starts with xen stuff... */ xen_start = hstart; } else if ( hvirt_start != 0xf5800000 ) { @@ -503,7 +503,7 @@ static int canonicalize_pagetable(unsign...

...ted = BLKIF_STATE_DISCONNECTED; INIT_WORK(&info->work, blkif_restart_queue); - for (i = 0; i < BLK_RING_SIZE; i++) + for (i = 0; i < BLK_MAX_RING_SIZE; i++) info->shadow[i].req.u.rw.id = i+1; - info->shadow[BLK_RING_SIZE-1].req.u.rw.id = 0x0fffffff; + info->shadow[BLK_MAX_RING_SIZE-1].req.u.rw.id = 0x0fffffff; /* Front end dir is a number, which is used as the id. */ info->handle = simple_strtoul(strrchr(dev->nodename, '/')+1, NULL, 0); dev_set_drvdata(&dev->dev, info); - err = tal...

...ted = BLKIF_STATE_DISCONNECTED; INIT_WORK(&info->work, blkif_restart_queue); - for (i = 0; i < BLK_RING_SIZE; i++) + for (i = 0; i < BLK_MAX_RING_SIZE; i++) info->shadow[i].req.u.rw.id = i+1; - info->shadow[BLK_RING_SIZE-1].req.u.rw.id = 0x0fffffff; + info->shadow[BLK_MAX_RING_SIZE-1].req.u.rw.id = 0x0fffffff; /* Front end dir is a number, which is used as the id. */ info->handle = simple_strtoul(strrchr(dev->nodename, '/')+1, NULL, 0); dev_set_drvdata(&dev->dev, info); - err = tal...

...ted = BLKIF_STATE_DISCONNECTED; INIT_WORK(&info->work, blkif_restart_queue); - for (i = 0; i < BLK_RING_SIZE; i++) + for (i = 0; i < BLK_MAX_RING_SIZE; i++) info->shadow[i].req.u.rw.id = i+1; - info->shadow[BLK_RING_SIZE-1].req.u.rw.id = 0x0fffffff; + info->shadow[BLK_MAX_RING_SIZE-1].req.u.rw.id = 0x0fffffff; /* Front end dir is a number, which is used as the id. */ info->handle = simple_strtoul(strrchr(dev->nodename, '/')+1, NULL, 0); dev_set_drvdata(&dev->dev, info); - err = tal...

...0 .org VIRT_ENTRY_OFFSET ENTRY(startup_xen) @@ -20,43 +20,7 @@ 1: jmp 1b # should never return .org HYPERCALL_PAGE_OFFSET ENTRY(hypercall_page) .skip 0x1000 - -/* - * __xen_guest information - */ -.macro utoa value - .if (\value) < 0 || (\value) >= 0x10 - utoa (((\value)>>4)&0x0fffffff) - .endif - .if ((\value) & 0xf) < 10 - .byte '0' + ((\value) & 0xf) - .else - .byte 'A' + ((\value) & 0xf) - 10 - .endif -.endm - -.section __xen_guest - .ascii "GUEST_OS=linux,GUEST_VER=2.6" - .ascii ",XEN_VER=xen-3.0" - .ascii ",VIRT_BAS...

>> + * __xen_guest information >> + */ >> +.macro utoa value >> + .if (\value) < 0 || (\value) >= 0x10 >> + utoa (((\value)>>4)&0x0fffffff) >> + .endif >> + .if ((\value) & 0xf) < 10 >> + .byte ''0'' + ((\value) & 0xf) >> + .else >> + .byte ''A'' + ((\value) & 0xf) - 10 >> + .endif >> +.endm > >Interesting macro abuse. Abuse? That'...

...x00000003,0x00000007,0x0000000f, - 0x0000001f,0x0000003f,0x0000007f,0x000000ff,0x000001ff, - 0x000003ff,0x000007ff,0x00000fff,0x00001fff,0x00003fff, - 0x00007fff,0x0000ffff,0x0001ffff,0x0003ffff,0x0007ffff, - 0x000fffff,0x001fffff,0x003fffff,0x007fffff,0x00ffffff, - 0x01ffffff,0x03ffffff,0x07ffffff,0x0fffffff,0x1fffffff, - 0x3fffffff,0x7fffffff,0xffffffff }; +#define MASK(b) ( (unsigned long)( (( (1<<((b)&31)) ^ (((b)&32)>>5) ) ) -1 ) \ + & 0xffffffff ) /* spans forward, skipping as many bytes as headend is negative; if headend is zero, simply finds next b...

...return ret; > + > + tmp = nv_rd32(device, 0x103c20); /* INTR */ > + if (tmp) > + nv_warn(priv, "Unexpected read from XTENSA.INTR: 0x%x", tmp); > + > + nv_wr32(device, 0x103d10, 0x1fffffff); /* ?? */ > + nv_wr32(device, 0x103d08, 0x0fffffff); /* ?? */ > + > + nv_wr32(device, 0x103d28, 0x90044); /* ?? */ > + nv_mask(device, 0x2090, 0xf0000000, 0x8 << 28); /* PFIFO.UNK90 */ > + nv_wr32(device, 0x103c20, 0x3f); /* INTR */ > + nv_wr32(device, 0x103d84, 0x3f); /* INTR_EN */ > + > + n...

...ect, NULL, 0x40000, 0x1000, 0, + &priv->gpu_fw); + if (ret) + return ret; + + tmp = nv_rd32(device, 0x103c20); /* INTR */ + if (tmp) + nv_warn(priv, "Unexpected read from XTENSA.INTR: 0x%x", tmp); + + nv_wr32(device, 0x103d10, 0x1fffffff); /* ?? */ + nv_wr32(device, 0x103d08, 0x0fffffff); /* ?? */ + + nv_wr32(device, 0x103d28, 0x90044); /* ?? */ + nv_mask(device, 0x2090, 0xf0000000, 0x8 << 28); /* PFIFO.UNK90 */ + nv_wr32(device, 0x103c20, 0x3f); /* INTR */ + nv_wr32(device, 0x103d84, 0x3f); /* INTR_EN */ + + nv_debug(priv, "Loading firmware to address: 0x%llx\n",...

...onfiguring [ 5.086726] pci 0000:00:03.0: bridge configuration invalid ([bus 00-00]), reconfiguring [ 5.094803] pci 0000:01:00.0: [10de:1d01] type 00 class 0x030000 [ 5.094834] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x00ffffff] [ 5.094846] pci 0000:01:00.0: reg 0x14: [mem 0x00000000-0x0fffffff 64bit pref] [ 5.094857] pci 0000:01:00.0: reg 0x1c: [mem 0x00000000-0x01ffffff 64bit pref] [ 5.094865] pci 0000:01:00.0: reg 0x24: [io 0x0000-0x007f] [ 5.094873] pci 0000:01:00.0: reg 0x30: [mem 0x00000000-0x0007ffff pref] [ 5.095001] pci 0000:01:00.0: vgaarb: VGA device added: decodes...

Hi Rusty, I had a look over your 011-paravirt-head.S.patch. I'm struggling to come up with a list of any benefits over having separate entrypoints for each hypervisor. Multiple entry pros: * allows maximum startup flexibility for any given hypervisor * for Xen at least, it's pretty simple * the "what hypervisor am I under" question is answered trivially cons:

...MPLE_MODE_MS4_CS12 0x00000009 -#define NV50_3D_MULTISAMPLE_MODE_MS8_CS8 0x0000000a +#define NV50_3D_MULTISAMPLE_MODE_MS8_CS8 0x0000000a #define NV50_3D_MULTISAMPLE_MODE_MS8_CS24 0x0000000b -#define NV50_3D_VERTEX_BEGIN_D3D 0x000015d4 -#define NV50_3D_VERTEX_BEGIN_D3D_PRIMITIVE__MASK 0x0fffffff +#define NV50_3D_VERTEX_BEGIN_D3D 0x000015d4 +#define NV50_3D_VERTEX_BEGIN_D3D_PRIMITIVE__MASK 0x0fffffff #define NV50_3D_VERTEX_BEGIN_D3D_PRIMITIVE__SHIFT 0 #define NV50_3D_VERTEX_BEGIN_D3D_PRIMITIVE_POINTS 0x00000001 -#define NV50_3D_VERTEX_BEGIN_D3D_PRIMITIVE_LINES 0x00000002 +#define...

...) + nv_wo32(xtensa->gpu_fw, i * 4, *((u32 *)fw->data + i)); + + release_firmware(fw); + + tmp = nv_ro32(xtensa, 0xc20); /* INTR */ + if (tmp) + nv_warn(xtensa, "Unexpected read from XTENSA.INTR: 0x%x", tmp); + + nv_wo32(xtensa, 0xd10, 0x1fffffff); /* ?? */ + nv_wo32(xtensa, 0xd08, 0x0fffffff); /* ?? */ + + nv_wo32(xtensa, 0xd28, xtensa->unkd28); /* ?? */ + nv_mask(xtensa, 0x2090, + 0xf << (xtensa->fifo_nibble * 4), + 0x8 << (xtensa->fifo_nibble * 4)); /* PFIFO.UNK90 */ + nv_wo32(xtensa, 0xc20, 0x3f); /* INTR */ + nv_wo32(xtensa, 0xd84, 0x3f); /* INTR_EN */ + + nv...

...copy (II) composite (RENDER acceleration) (==) intel(0): Backing store disabled (==) intel(0): Silken mouse enabled (II) intel(0): Initializing HW Cursor (II) intel(0): Fixed memory allocation layout: (II) intel(0): 0x006ff000: end of stolen memory (II) intel(0): 0x006ff000-0x0fffffff: DRI memory manager (254980 kB) (II) intel(0): 0x10000000: end of aperture (II) intel(0): BO memory allocation layout: (II) intel(0): 0x006ff000: start of memory manager (II) intel(0): 0x00800000-0x00ffffff: front buffer (8192 kB) X tiled (II) intel(0): 0x01000000-0x01000fff:...

...loppy->fat_entries, 4); + if (floppy->fat == NULL) { + nbdkit_error ("calloc: %m"); + return -1; + } + + /* Populate the FAT. First two entries are reserved and + * contain standard data. + */ + floppy->fat[0] = htole32 (0x0ffffff8); + floppy->fat[1] = htole32 (0x0fffffff); + + for (i = 0; i < floppy->nr_dirs; ++i) { + write_fat_file (floppy->dirs[i].first_cluster, + floppy->dirs[i].nr_clusters, floppy); + } + for (i = 0; i < floppy->nr_files; ++i) { + write_fat_file (floppy->files[i].first_cluster, +...

The Geforce 9800GT also shows different behaviour without nvidiafb in the kernel. I get lengthy messages from nouveau, like the ones found in the email attachment. It also eventually gets into the lightdm login graphical screen, but with this card the screen is highly distorted, despite the mouse cursor being properly displayed and moving around properly. Luis On Thu, Jan 25, 2018 at 1:14 PM,

...@@ -868,24 +1278,6 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NVC0_3D_MULTISAMPLE_MODE_MS8_CS8 0x0000000a #define NVC0_3D_MULTISAMPLE_MODE_MS8_CS24 0x0000000b -#define NVC0_3D_VERTEX_BEGIN_D3D 0x000015d4 -#define NVC0_3D_VERTEX_BEGIN_D3D_PRIMITIVE__MASK 0x0fffffff -#define NVC0_3D_VERTEX_BEGIN_D3D_PRIMITIVE__SHIFT 0 -#define NVC0_3D_VERTEX_BEGIN_D3D_PRIMITIVE_POINTS 0x00000001 -#define NVC0_3D_VERTEX_BEGIN_D3D_PRIMITIVE_LINES 0x00000002 -#define NVC0_3D_VERTEX_BEGIN_D3D_PRIMITIVE_LINE_STRIP 0x00000003 -#define NVC0_3D_VERTEX_BEGIN_D3D_PRIMITIVE_TRIANGLES...

...re: registered new device driver usb [ 1.766600] EDAC MC: Ver: 3.0.0 [ 1.766921] Advanced Linux Sound Architecture Driver Initialized. [ 1.767039] PCI: Using ACPI for IRQ routing [ 1.767100] PCI: pci_cache_line_size set to 32 bytes [ 1.767150] e820: reserve RAM buffer [mem 0x0dff0000-0x0fffffff] [ 1.767606] Switching to clocksource refined-jiffies [ 1.773267] pnp: PnP ACPI init [ 1.773355] ACPI: bus type PNP registered [ 1.773821] system 00:00: [mem 0x000f0000-0x000f3fff] could not be reserved [ 1.773882] system 00:00: [mem 0x000f4000-0x000f7fff] could not be reserved [...

Add nbdkit-floppy-plugin, “inspired” by qemu's VVFAT driver, but without the ability to handle writes. The implementation is pretty complete, supporting FAT32, LFNs, volume labels, timestamps, etc, and it passes both ‘make check’ and ‘make check-valgrind’. Usage is simple; to serve the current directory: $ nbdkit floppy . Then using guestfish (or any NBD client): $ guestfish --ro