search for: 0x0184

...au/core/engine/graph/nvc0.c > +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c > @@ -894,6 +894,10 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base, > nv_wr32(priv, fuc_base + 0x0188, i >> 6); > nv_wr32(priv, fuc_base + 0x0184, code->data[i]); > } > + > + /* code must be padded to 0x40 bytes */ > + for (; i & 0x3f; i++) > + nv_wr32(priv, fuc_base + 0x0184, 0); > } > > static void > -- > 1.9.2 > > _______________________________________________...

...return 1; +} + static struct nouveau_pgraph_object_method nv04_graph_mthds_sw[] = { { 0x0150, nv04_graph_mthd_set_ref }, {} }; -static struct nouveau_pgraph_object_method nv04_graph_mthds_set_operation[] = { +static struct nouveau_pgraph_object_method nv04_graph_mthds_nv03_gdirect[] = { + { 0x0184, nv04_graph_mthd_bind_nv01_patt }, + { 0x0188, nv04_graph_mthd_bind_rop }, + { 0x018c, nv04_graph_mthd_bind_beta1 }, + { 0x0190, nv04_graph_mthd_bind_surf_dst }, + { 0x02fc, nv04_graph_mthd_set_operation }, + {}, +}; + +static struct nouveau_pgraph_object_method nv04_graph_mthds_nv04_gdirect[] = {...

Signed-off-by: Marcin Ko?cielnicki <koriakin at 0x04.net> --- drivers/gpu/drm/nouveau/nv04_fbcon.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/gpu/drm/nouveau/nv04_fbcon.c b/drivers/gpu/drm/nouveau/nv04_fbcon.c index 813b25c..7cf9287 100644 --- a/drivers/gpu/drm/nouveau/nv04_fbcon.c +++ b/drivers/gpu/drm/nouveau/nv04_fbcon.c @@ -236,7 +236,7 @@

...[ 477.641881] [drm] PGRAPH_ERROR - nSource: PROTECTION_ERROR, nStatus: [ 477.641890] [drm] PGRAPH_ERROR - Ch 2/2 Class 0x8297 Mthd 0x15e0 Data 0x00000000:0x00000000 [ 477.641944] [drm] PGRAPH_ERROR - nSource: PROTECTION_ERROR, nStatus: [ 477.641954] [drm] PGRAPH_ERROR - Ch 2/1 Class 0x5039 Mthd 0x0184 Data 0x00000000:0x00000e00 [ 477.642004] [drm] PGRAPH_ERROR - nSource: PROTECTION_ERROR, nStatus: [ 477.642013] [drm] PGRAPH_ERROR - Ch 2/1 Class 0x5039 Mthd 0x0184 Data 0x00000000:0x00000e00 [ 477.642066] [drm] PGRAPH_ERROR - nSource: PROTECTION_ERROR, nStatus: [ 477.642074] [drm] PGRAPH_ERROR...

...au/core/engine/graph/nvc0.c > +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c > @@ -768,6 +768,10 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base, > nv_wr32(priv, fuc_base + 0x0188, i >> 6); > nv_wr32(priv, fuc_base + 0x0184, code->data[i]); > } > + > + /* code must be padded to 0x40 */ > + for (; i < (((code->size / 4) + 0x3f) & ~0x3f); i++) "for (; i & 0x3f; i++)" would work just as well :) > + nv_wr32(priv, fuc_base + 0x0184, 0); > } &g...

...5760..367e72daf8b1 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c @@ -768,6 +768,10 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base, nv_wr32(priv, fuc_base + 0x0188, i >> 6); nv_wr32(priv, fuc_base + 0x0184, code->data[i]); } + + /* code must be padded to 0x40 */ + for (; i < (((code->size / 4) + 0x3f) & ~0x3f); i++) + nv_wr32(priv, fuc_base + 0x0184, 0); } static void -- 1.9.1

...9988..013475c62986 100644 --- a/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c @@ -894,6 +894,10 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base, nv_wr32(priv, fuc_base + 0x0188, i >> 6); nv_wr32(priv, fuc_base + 0x0184, code->data[i]); } + + /* code must be padded to 0x40 bytes */ + for (; i & 0x3f; i++) + nv_wr32(priv, fuc_base + 0x0184, 0); } static void -- 1.9.2

...raph/nvc0.c >> +++ b/drivers/gpu/drm/nouveau/core/engine/graph/nvc0.c >> @@ -894,6 +894,10 @@ nvc0_graph_init_fw(struct nvc0_graph_priv *priv, u32 fuc_base, >> nv_wr32(priv, fuc_base + 0x0188, i >> 6); >> nv_wr32(priv, fuc_base + 0x0184, code->data[i]); >> } >> + >> + /* code must be padded to 0x40 bytes */ >> + for (; i & 0x3f; i++) >> + nv_wr32(priv, fuc_base + 0x0184, 0); It's 256 bytes indeed. >> } >> >> static void >> -- >...

...l; + const int sub = NvSubCtxSurf2D; int surface_fmt, pattern_fmt, rect_fmt; int ret; @@ -247,25 +248,25 @@ nv04_fbcon_accel_init(struct fb_info *info) return 0; } - BEGIN_RING(chan, 1, 0x0000, 1); + BEGIN_RING(chan, sub, 0x0000, 1); OUT_RING(chan, NvCtxSurf2D); - BEGIN_RING(chan, 1, 0x0184, 2); + BEGIN_RING(chan, sub, 0x0184, 2); OUT_RING(chan, NvDmaFB); OUT_RING(chan, NvDmaFB); - BEGIN_RING(chan, 1, 0x0300, 4); + BEGIN_RING(chan, sub, 0x0300, 4); OUT_RING(chan, surface_fmt); OUT_RING(chan, info->fix.line_length | (info->fix.line_length << 16)); OUT_RING(chan, i...

...ond I'll attach a screenshot of my screen after about 10-15 minutes. The kernel (log to be attached as well) is screaming like this: [drm] nouveau 0000:01:00.0: PGRAPH_ERROR - nSource: PROTECTION_ERROR, nStatus: INVALID_STATE [drm] nouveau 0000:01:00.0: PGRAPH_ERROR - Ch 1/0 Class 0x0039 Mthd 0x0184 Data 0x000011ce:0x000011ce My system: $ X -version X.Org X Server 1.7.1 Release Date: 2009-10-23 X Protocol Version 11, Revision 0 Build Operating System: 2.6.18-164.2.1.el5 Current Operating System: Linux sedan 2.6.31.5-127.fc12.i686.PAE #1 SMP Sat Nov 7 21:25:57 EST 2009 i686 Kernel command...

...m kernel: [drm] nouveau 0000:01:00.0: PFIFO_CACHE_ERROR - Ch 2/2 Mthd 0x0180 Data 0x88000000 May 1 09:46:31 lithium kernel: [drm] nouveau 0000:01:00.0: PFIFO_CACHE_ERROR - Ch 2/3 Mthd 0x0000 Data 0x88000002 May 1 09:46:31 lithium kernel: [drm] nouveau 0000:01:00.0: PFIFO_CACHE_ERROR - Ch 2/3 Mthd 0x0184 Data 0xbeef0201 May 1 09:46:31 lithium kernel: [drm] nouveau 0000:01:00.0: PFIFO_CACHE_ERROR - Ch 2/3 Mthd 0x0188 Data 0xbeef0201 May 1 09:46:31 lithium kernel: [drm] nouveau 0000:01:00.0: PFIFO_CACHE_ERROR - Ch 2/4 Mthd 0x0000 Data 0x88000003 May 1 09:46:31 lithium kernel: [drm] nouveau 0000:01...

Hi everyone, Way overdue v2 of the final patches that enable basic GK20A support. Hopefully all the issues raised with v1 have been addressed. Changes since v1: - Use gk20a clock driver by Ben instead of twiddling nv04's - Name new classes after gk20a instead of nvea - Addressed comments about BAR initialization code factorization - Removed non-essential code which only purpose was to avoid

...oesn't. In both cases I need to restart the machine remotely. Today I finally got something that might be helpful in /var/log/messages: Sep 17 08:03:26 localhost kernel: usb 2-2: USB disconnect, address 7 Sep 17 17:25:08 localhost kernel: nouveau 0000:05:00.0: PFIFO_CACHE_ERROR - Ch 1/7 Mthd 0x0184 Data 0xd8000002 Sep 17 17:25:08 localhost kernel: nouveau 0000:05:00.0: PFIFO_CACHE_ERROR - Ch 1/7 Mthd 0x0188 Data 0xd8000001 Sep 17 17:25:08 localhost kernel: nouveau 0000:05:00.0: PGRAPH_ERROR - nSource: DMA_W_PROTECTION, nStatus: PROTECTION_FAULT Sep 17 17:25:08 localhost kernel: nouveau 0000:0...

...ngth = 0xa0 DataHandle = 0x163 Flags = 0x0 Data64 = 0x0 > ISDN1#02: too much voice to send for NCCI=0x10101 > ISDN1#02: too much voice to send for NCCI=0x10101 DATA_B3_IND ID=002 #0x0184 LEN=0030 Controller/PLCI/NCCI = 0x10101 Data32 = 0x40ac436a DataLength = 0xa0 DataHandle = 0xb Flags = 0x0 Data64 = 0x0 DATA_B3_RESP ID=002 #0x0184 LEN=0014...

https://bugs.freedesktop.org/show_bug.cgi?id=48434 Bug #: 48434 Summary: X freezes with "EQ overflowing" Classification: Unclassified Product: xorg Version: unspecified Platform: x86-64 (AMD64) OS/Version: Linux (All) Status: NEW Severity: critical Priority: medium Component:

Hi everyone, Here is the second batch of patches to add GK20A support to Nouveau. This time we are adding the actual chip support, and this series brings the driver to a point where a slightly-tweaked Mesa successfully runs shaders and renders triangles on GBM! Many thanks to Thierry Reding and the people on the #nouveau IRC channel for their help without which we would not have reached this

http://bugs.freedesktop.org/show_bug.cgi?id=20130 Summary: GT200: nv50 chipset 0xa0 lockup Product: xorg Version: git Platform: x86-64 (AMD64) OS/Version: Linux (All) Status: NEW Severity: normal Priority: medium Component: Driver/nouveau AssignedTo: nouveau at lists.freedesktop.org

Latest patches for GK20A, taking comments received for v3 into account. Changes since v3: - use only pfn_to_page() and page_to_pfn() in GK20A's FB. These functions are present on every arch and the physical address to page frame number conversion is also consistently a shift of PAGE_SHIFT. This part will probably be replaced by something nicer in the future anyway. - fixed a warning on

Changes since v2: - Enabled software class - Removed unneeded changes to nouveau_accel_init() - Replaced use of architecture-private pfn_to_dma() and dma_to_pfn() with the portable page_to_phys()/phys_to_page() - Fixed incorrect comment/commit log talking about bytes instead of words Hope this looks good! Once this gets merged the next set will be to use this driver on Jetson and Venice2

This was the first step of the secure boot refactoring - as Ben asked for some fixes, I now submit it as its own series to make it easier to review (and also because rebasing secure boot on top of this takes time and I don't want to do it until this is validated!). This series attempts to factorize the duplicate falcon-related code into a single library, using the existing nvkm_falcon