Displaying 3 results from an estimated 3 matches for "0x0010a044".
Did you mean:
0x0010a004
2015 Mar 11
0
[PATCH] pmu/gk20a: PMU boot support.
...tate_r : 0x%x\n",
> + nv_rd32(ppmu, 0x0010a04c));
> + nv_debug(ppmu, "pmu_falcon_mailbox0_r : 0x%x\n",
> + nv_rd32(ppmu, 0x0010a040));
> + nv_debug(ppmu, "pmu_falcon_mailbox1_r : 0x%x\n",
> + nv_rd32(ppmu, 0x0010a044));
> + nv_debug(ppmu, "pmu_falcon_irqstat_r : 0x%x\n",
> + nv_rd32(ppmu, 0x0010a008));
> + nv_debug(ppmu, "pmu_falcon_irqmode_r : 0x%x\n",
> + nv_rd32(ppmu, 0x0010a00c));
> + nv_debug(ppmu, "pmu_falcon_irqmask_r :...
2015 Mar 11
3
[PATCH] pmu/gk20a: PMU boot support.
...uot;,
+ nv_rd32(ppmu, 0x0010a100));
+ nv_debug(ppmu, "pmu_falcon_idlestate_r : 0x%x\n",
+ nv_rd32(ppmu, 0x0010a04c));
+ nv_debug(ppmu, "pmu_falcon_mailbox0_r : 0x%x\n",
+ nv_rd32(ppmu, 0x0010a040));
+ nv_debug(ppmu, "pmu_falcon_mailbox1_r : 0x%x\n",
+ nv_rd32(ppmu, 0x0010a044));
+ nv_debug(ppmu, "pmu_falcon_irqstat_r : 0x%x\n",
+ nv_rd32(ppmu, 0x0010a008));
+ nv_debug(ppmu, "pmu_falcon_irqmode_r : 0x%x\n",
+ nv_rd32(ppmu, 0x0010a00c));
+ nv_debug(ppmu, "pmu_falcon_irqmask_r : 0x%x\n",
+ nv_rd32(ppmu, 0x0010a018));
+ nv_debug(ppmu, "...
2015 Mar 12
2
[PATCH] pmu/gk20a: PMU boot support.
...tate_r : 0x%x\n",
> + nv_rd32(ppmu, 0x0010a04c));
> + nv_debug(ppmu, "pmu_falcon_mailbox0_r : 0x%x\n",
> + nv_rd32(ppmu, 0x0010a040));
> + nv_debug(ppmu, "pmu_falcon_mailbox1_r : 0x%x\n",
> + nv_rd32(ppmu, 0x0010a044));
> + nv_debug(ppmu, "pmu_falcon_irqstat_r : 0x%x\n",
> + nv_rd32(ppmu, 0x0010a008));
> + nv_debug(ppmu, "pmu_falcon_irqmode_r : 0x%x\n",
> + nv_rd32(ppmu, 0x0010a00c));
> + nv_debug(ppmu, "pmu_falcon_irqmask_r :...