search for: 0x00000fff

From: Xia Yang <xiay at nvidia.com> Fix the channel id bit mask in FIFO schedule timeout error handling. FIFO_ENGINE_STATUS_NEXT_ID is bit 27:16 thus 0x0fff0000. FIFO_ENGINE_STATUS_ID is bit 11:0 thus 0x00000fff. Signed-off-by: Xia Yang <xiay at nvidia.com> Reviewed-by: Alexandre Courbot <acourbot at nvidia.com> --- drm/nouveau/nvkm/engine/fifo/gk104.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drm/nouveau/nvkm/engine/fifo/gk104.c b/drm/nouveau/nvkm/engine/fifo/gk...

...oiset + */ +#include "priv.h" + +static int +gf117_ibus_init(struct nvkm_subdev *ibus) +{ + struct nvkm_device *device = ibus->device; + nvkm_mask(device, 0x122310, 0x0003ffff, 0x00000800); + nvkm_mask(device, 0x122348, 0x0003ffff, 0x00000100); + nvkm_mask(device, 0x1223b0, 0x0003ffff, 0x00000fff); + return 0; +} + +static const struct nvkm_subdev_func +gf117_ibus = { + .init = gf117_ibus_init, + .intr = gf100_ibus_intr, +}; + +int +gf117_ibus_new(struct nvkm_device *device, int index, + struct nvkm_subdev **pibus) +{ + struct nvkm_subdev *ibus; + if (!(ibus = *pibus = kzalloc(sizeof...

...wise.c (revision 3086) +++ bitwise.c (working copy) @@ -23,14 +23,8 @@ #include "misc.h" #include "ogg.h" -static unsigned long mask[]= -{0x00000000,0x00000001,0x00000003,0x00000007,0x0000000f, - 0x0000001f,0x0000003f,0x0000007f,0x000000ff,0x000001ff, - 0x000003ff,0x000007ff,0x00000fff,0x00001fff,0x00003fff, - 0x00007fff,0x0000ffff,0x0001ffff,0x0003ffff,0x0007ffff, - 0x000fffff,0x001fffff,0x003fffff,0x007fffff,0x00ffffff, - 0x01ffffff,0x03ffffff,0x07ffffff,0x0fffffff,0x1fffffff, - 0x3fffffff,0x7fffffff,0xffffffff }; +#define MASK(b) ( (unsigned long)( (( (1<<((b)&31)) ^...

...Context(context), "0x0000000f0000ffff", 16); This is working properly as expected. However I have noticed that if the bits are not prefixed with enough zeros to correspond to 32 or 64 bits this gives me: For 0x0fff := 0xffffffff0fff (incorrect) For 0xfff := 0xfffffffffff (incorrect) For 0x00000fff := 0xffffffff00000fff (incorrect) For 0x0000fff := 0xffffffff0000fff (incorrect) For 0xffffffff := 0xffffffffffffffff (incorrect) For 0x00000000ffffffff := 0xffffffff (correct) For 0xffffffffff := 0xffffffffffffffff (incorrect) I hope that is sufficient data. I explored the code a bit and found th...

Hello, Attached a small patch that correctly identifies the DLLoff bit for >=GF100. Marked RFC because I haven't seen any GDDR5 samples that *enable* the DLL. I'd like to verify whether the DLL should be reset when enabled. Could increase likelihood of succesfull reclock. Ben: could you do some experiments with this bit to see if GDDR5 needs some DLL reset logic? Thanks, and happy

Hi all, I recently bought a Intel D2500HN motherboard with Intel GMA 3600 video card. I want to install FreeBSD 9-Release on it via PXE, but after booting the system, it seems that video card driver doesn't work properly. Have a look at this picture: http://img703.imageshack.us/img703/5648/20120714393.jpg I've tried the # vidcontrol 80x25 but unfortunately it doesn't help. Do

Hi All, This series implements using double immediates in the nouveau codegen code. This turns the following (nvc0) code: 1: mov u32 $r2 0x00000000 (8) 2: mov u32 $r3 0x3fe00000 (8) 3: add f64 $r0d $r0d $r2d (8) Into: 1: add f64 $r0d $r0d 0.500000 (8) This has been tested with the 2 double shader tests which I just send to the piglet list. On a gk208 (gk110 / SM35)

.... done. Jan 20 17:42:15 laptop kernel: Freezing user space processes ... (elapsed 0.264 seconds) done. Jan 20 17:42:15 laptop kernel: Double checking all user space processes after OOM killer disable... (elapsed 0.000 seconds) Jan 20 17:42:15 laptop kernel: PM: Marking nosave pages: [mem 0x00000000-0x00000fff] Jan 20 17:42:15 laptop kernel: PM: Marking nosave pages: [mem 0x0009d000-0x000fffff] Jan 20 17:42:15 laptop kernel: PM: Marking nosave pages: [mem 0x48b7f000-0x49ffefff] Jan 20 17:42:15 laptop kernel: PM: Marking nosave pages: [mem 0x4a000000-0xffffffff] Jan 20 17:42:15 laptop kernel: PM: Basic me...

...5 #define NVC0_3D_ALPHA_TEST_FUNC_GEQUAL 0x00000206 #define NVC0_3D_ALPHA_TEST_FUNC_ALWAYS 0x00000207 -#define NVC0_3D_DRAW_TFB_STRIDE 0x00001318 +#define NVC0_3D_DRAW_TFB_STRIDE 0x00001318 #define NVC0_3D_DRAW_TFB_STRIDE__MIN 0x00000001 #define NVC0_3D_DRAW_TFB_STRIDE__MAX 0x00000fff -#define NVC0_3D_BLEND_COLOR(i0) (0x0000131c + 0x4*(i0)) +#define NVC0_3D_BLEND_COLOR(i0) (0x0000131c + 0x4*(i0)) #define NVC0_3D_BLEND_COLOR__ESIZE 0x00000004 #define NVC0_3D_BLEND_COLOR__LEN 0x00000004 @@ -884,6 +975,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALIN...

...mem 0x0000000100000000-0x00000010317fffff] usable [ 0.000000] NX (Execute Disable) protection: active [ 0.000000] SMBIOS 3.0 present. [ 0.000000] DMI: FUJITSU D3401-H1/D3401-H1, BIOS V5.0.0.11 R1.7.0.SR.2 for D3401-H1x 11/25/2015 [ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved [ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable [ 0.000000] e820: last_pfn = 0x1031800 max_arch_pfn = 0x400000000 [ 0.000000] MTRR default type: write-back [ 0.000000] MTRR fixed ranges enabled: [ 0.000000] 00000-9FFFF write-back [ 0.000000]...

...0 #define NV50_3D_VTX_ATTR_4NB_X__MASK 0x000000ff @@ -291,7 +291,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. #define NV50_3D_VERTEX_ARRAY_FETCH__ESIZE 0x00000010 #define NV50_3D_VERTEX_ARRAY_FETCH__LEN 0x00000010 #define NV50_3D_VERTEX_ARRAY_FETCH_STRIDE__MASK 0x00000fff -#define NV50_3D_VERTEX_ARRAY_FETCH_STRIDE__SHIFT 0 +#define NV50_3D_VERTEX_ARRAY_FETCH_STRIDE__SHIFT 0 #define NV50_3D_VERTEX_ARRAY_FETCH_ENABLE 0x20000000 #define NV50_3D_VERTEX_ARRAY_START_HIGH(i0) (0x00000904 + 0x10*(i0)) @@ -302,7 +302,7 @@ WITH THE SOFTWARE OR THE USE OR OTHE...

On Wed, 2016-02-03 at 15:28 -0500, Konrad Rzeszutek Wilk wrote: > > > And I wonder if the XEN_DOMCTL_irq_permission aka, > > > xc_domain_irq_permission > > > had been called. I remember that at some point we missed it for > > > Xend.. > > > > > False alarm. > > It was all in Linux. Attached are four patches (the first two > are for

...5 #define NVC0_3D_ALPHA_TEST_FUNC_GEQUAL 0x00000206 #define NVC0_3D_ALPHA_TEST_FUNC_ALWAYS 0x00000207 -#define NVC0_3D_DRAW_TFB_STRIDE 0x00001318 +#define NVC0_3D_DRAW_TFB_STRIDE 0x00001318 #define NVC0_3D_DRAW_TFB_STRIDE__MIN 0x00000001 #define NVC0_3D_DRAW_TFB_STRIDE__MAX 0x00000fff -#define NVC0_3D_BLEND_COLOR(i0) (0x0000131c + 0x4*(i0)) +#define NVC0_3D_BLEND_COLOR(i0) (0x0000131c + 0x4*(i0)) #define NVC0_3D_BLEND_COLOR__ESIZE 0x00000004 #define NVC0_3D_BLEND_COLOR__LEN 0x00000004 @@ -597,8 +973,11 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALI...

...0000] MPTABLE: APIC at: 0xFEE00000 [ 0.000000] Processor #0 (Bootup-CPU) [ 0.000000] IOAPIC[0]: apic_id 0, version 17, address 0xfec00000, GSI 0-23 [ 0.000000] Processors: 1 [ 0.000000] smpboot: Allowing 1 CPUs, 0 hotplug CPUs [ 0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff] [ 0.000000] PM: Registered nosave memory: [mem 0x0009f000-0x0009ffff] [ 0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000effff] [ 0.000000] PM: Registered nosave memory: [mem 0x000f0000-0x000fffff] [ 0.000000] e820: [mem 0x1f400000-0xfeffbfff] available for PCI devices [...

...ine MAC16_16(c,a,b) (ADD32((c),MULT16_16((a),(b)))) static inline spx_word32_t MAC16_16(spx_word32_t w, spx_word16_t x, spx_word16_t y) { long res; res = w + ((long) x * (long) y); return(res); } //#define MULT16_32_Q12(a,b) ADD32(MULT16_16((a),SHR((b),12)), SHR(MULT16_16((a),((b)&0x00000fff)),12)) static inline spx_word32_t MULT16_32_Q12(spx_word16_t a, spx_word32_t b) { // long res, tmp, tmp2; // tmp = ((long) x) * (y >> 12); // tmp2 = ((long) x * (y & 0x00000fff)) >> 12; // res = tmp + tmp2; // return(res); return(ADD32(MULT16_16((a),SHR((b),12)), SHR(MULT...

...f] reserved [ 0.000000] Xen: [mem 0x00000000fec00000-0x00000000feefffff] reserved [ 0.000000] Xen: [mem 0x00000000ff800000-0x00000000ffffffff] reserved [ 0.000000] NX (Execute Disable) protection: active [ 0.000000] DMI not present or invalid. [ 0.000000] e820: update [mem 0x00000000-0x00000fff] usable ==> reserved [ 0.000000] e820: remove [mem 0x000a0000-0x000fffff] usable [ 0.000000] AGP: No AGP bridge found [ 0.000000] e820: last_pfn = 0x8000 max_arch_pfn = 0x400000000 [ 0.000000] Base memory trampoline at [ffff88000009a000] 9a000 size 24576 [ 0.000000] init_memory_ma...

...0000] MPTABLE: APIC at: 0xFEE00000 [ 0.000000] Processor #0 (Bootup-CPU) [ 0.000000] IOAPIC[0]: apic_id 0, version 17, address 0xfec00000, GSI 0-23 [ 0.000000] Processors: 1 [ 0.000000] smpboot: Allowing 1 CPUs, 0 hotplug CPUs [ 0.000000] PM: Registered nosave memory: [mem 0x00000000-0x00000fff] [ 0.000000] PM: Registered nosave memory: [mem 0x0009f000-0x0009ffff] [ 0.000000] PM: Registered nosave memory: [mem 0x000a0000-0x000effff] [ 0.000000] PM: Registered nosave memory: [mem 0x000f0000-0x000fffff] [ 0.000000] e820: [mem 0x1f400000-0xfeffbfff] available for PCI devices [...

https://bugs.freedesktop.org/show_bug.cgi?id=109681 Bug ID: 109681 Summary: Nvidia GT710 => nouveau + wayland + swayWM => crash when use acceleration (open Firefox) Product: Mesa Version: 18.3 Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW Severity: critical

...You might have to change the root device from /dev/hd[a-d] to /dev/xvd[a-d] in your root= kernel command line option Dec 29 23:55:59 xen kernel: HVMOP_pagetable_dying not supported Dec 29 23:55:59 xen kernel: e820: update [mem 0x00000000-0x00000fff] usable ==> reserved Dec 29 23:55:59 xen kernel: e820: remove [mem 0x000a0000-0x000fffff] usable Dec 29 23:55:59 xen kernel: AGP: No AGP bridge found Dec 29 23:55:59 xen kernel: e820: last_pfn = 0x7f7ff max_arch_pfn = 0x400000000 Dec 29 23:55:59 xen kernel: MTRR default type: write-back Dec 29 2...

Hi All, I been using virt-builder to create testing VMs (most ubuntu) for a while, and it works great. But when I cloned the git repo today and found the process becoming extremely slow, please see the output below. log that produced by pre-installed vendor package: virt-builder ubuntu-14.04 --firstboot-command 'useradd -m -p "" myan; chage -d 0 myan; usermod -aG sudo myan;' [