Displaying 13 results from an estimated 13 matches for "0x000000000".
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0x00000000
2016 Oct 27
2
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...SO_QUALITY_2 |
> + (pitch >> 5));
> + PUSH_DATA(push, GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
> + GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
> + (width - 1));
> + PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS | (height - 1));
> + PUSH_DATA(push, 0x000000000);
> + PUSH_DATA(push, 0x000000000);
> + }
> + }
> +}
> +
> #endif
> diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
> index a53dfe6..017a7da 100644
> --- a/src/nvc0_exa.c
> +++ b/src/nvc0_exa.c
> @@ -532,20 +532,13 @@ NVC0EXACheckTexture(PicturePtr ppict, PicturePt...
2015 Nov 05
0
[PATCH] nvkm: add/remove 0's to make 7 (or 9)-nibble constants use 8 nibbles
...04.c
@@ -216,11 +216,11 @@ r1373f4_fini(struct gk104_ramfuc *fuc)
ram_wr32(fuc, 0x1373ec, tmp | (v1 << 16));
ram_mask(fuc, 0x1373f0, (~ram->mode & 3), 0x00000000);
if (ram->mode == 2) {
- ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000002);
- ram_mask(fuc, 0x1373f4, 0x00001100, 0x000000000);
+ ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000002);
+ ram_mask(fuc, 0x1373f4, 0x00001100, 0x00000000);
} else {
- ram_mask(fuc, 0x1373f4, 0x00000003, 0x000000001);
- ram_mask(fuc, 0x1373f4, 0x00010000, 0x000000000);
+ ram_mask(fuc, 0x1373f4, 0x00000003, 0x00000001);
+ ram_mask(fuc, 0x1373f...
2016 Oct 17
2
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...SO_QUALITY_2 |
> + (pitch >> 5));
> + PUSH_DATA(push, GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
> + GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
> + (width - 1));
> + PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS | (height - 1));
> + PUSH_DATA(push, 0x000000000);
> + PUSH_DATA(push, 0x000000000);
> + }
> + }
> +}
> +
> #endif
> diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
> index a53dfe6..c8ace97 100644
> --- a/src/nvc0_exa.c
> +++ b/src/nvc0_exa.c
> @@ -538,14 +538,8 @@ NVC0EXAPictSolid(NVPtr pNv, PicturePtr ppict, un...
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...ER_SIZE_SAMPLER_COLOR |
>> +
>> GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
>> + (width - 1));
>> + PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS |
>> (height - 1));
>> + PUSH_DATA(push, 0x000000000);
>> + PUSH_DATA(push, 0x000000000);
>> + }
>> + }
>> +}
>> +
>> #endif
>> diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
>> index a53dfe6..017a7da 100644
>> --- a/src/nvc0_exa.c
>> +++ b/src/nvc0_e...
2016 Oct 16
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...ATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
+ (pitch >> 5));
+ PUSH_DATA(push, GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
+ GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
+ (width - 1));
+ PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS | (height - 1));
+ PUSH_DATA(push, 0x000000000);
+ PUSH_DATA(push, 0x000000000);
+ }
+ }
+}
+
#endif
diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
index a53dfe6..c8ace97 100644
--- a/src/nvc0_exa.c
+++ b/src/nvc0_exa.c
@@ -538,14 +538,8 @@ NVC0EXAPictSolid(NVPtr pNv, PicturePtr ppict, unsigned unit)
PUSH_DATAu(push, pNv->scratch, SOLID(...
2016 Oct 27
0
[PATCH v2 5/7] nvc0: refactor TIC uploads to allow different specifics per generation
...ATA(push, GM107_TIC2_3_LOD_ANISO_QUALITY_2 |
+ (pitch >> 5));
+ PUSH_DATA(push, GM107_TIC2_4_BORDER_SIZE_SAMPLER_COLOR |
+ GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
+ (width - 1));
+ PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS | (height - 1));
+ PUSH_DATA(push, 0x000000000);
+ PUSH_DATA(push, 0x000000000);
+ }
+ }
+}
+
#endif
diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
index a53dfe6..017a7da 100644
--- a/src/nvc0_exa.c
+++ b/src/nvc0_exa.c
@@ -532,20 +532,13 @@ NVC0EXACheckTexture(PicturePtr ppict, PicturePtr pdpict, int op)
static Bool
NVC0EXAPictSolid(NVPtr...
2016 Oct 17
0
[PATCH 4/5] nvc0: refactor TIC uploads to allow different specifies per generation
...ER_SIZE_SAMPLER_COLOR |
>> +
>> GM107_TIC2_4_TEXTURE_TYPE_TWO_D_NO_MIPMAP |
>> + (width - 1));
>> + PUSH_DATA(push, GM107_TIC2_5_NORMALIZED_COORDS |
>> (height - 1));
>> + PUSH_DATA(push, 0x000000000);
>> + PUSH_DATA(push, 0x000000000);
>> + }
>> + }
>> +}
>> +
>> #endif
>> diff --git a/src/nvc0_exa.c b/src/nvc0_exa.c
>> index a53dfe6..c8ace97 100644
>> --- a/src/nvc0_exa.c
>> +++ b/src/nvc0_e...
2012 Apr 12
1
6.2 x86_64 "mtrr_cleanup: can not find optimal value"
...11 17:25:36 kernel: mtrr_cleanup: can not find optimal value
Apr 11 17:25:36 kernel: please specify mtrr_gran_size/mtrr_chunk_size
cat /proc/mtrr
reg00: base=0x0d0000000 ( 3328MB), size= 256MB, count=1: uncachable
reg01: base=0x0e0000000 ( 3584MB), size= 512MB, count=1: uncachable
reg02: base=0x000000000 ( 0MB), size= 8192MB, count=1: write-back
reg03: base=0x200000000 ( 8192MB), size= 512MB, count=1: write-back
reg04: base=0x220000000 ( 8704MB), size= 256MB, count=1: write-back
reg05: base=0x0cf700000 ( 3319MB), size= 1MB, count=1: uncachable
reg06: base=0x0cf800000 ( 3320MB), size= 8MB...
2007 Apr 18
1
[Bridge] Bridge not bridging NFS fragments?
...mpting to talk NFS with each other, the
machine on the left sends a read request, which is bridged, and the
machine on the right sends a fragmented UDP packet of 8K, this is as
observed on eth0:
14:33:59.320397 192.168.0.49.1749359354 > 192.168.0.2.2049: 108 read fh 985,985790/5042 8192 bytes @ 0x000000000
14:33:59.321676 192.168.0.2.2049 > 192.168.0.49.1749359354: reply ok 1472 read (frag 8235:1480@0+)
14:33:59.321798 192.168.0.2 > 192.168.0.49: (frag 8235:1480@1480+)
14:33:59.321922 192.168.0.2 > 192.168.0.49: (frag 8235:1480@2960+)
14:33:59.322044 192.168.0.2 > 192.168.0.49: (frag 8235...
2013 Sep 11
39
[Bug 69203] New: Kernel 3.11 - Xorg hangs immediately after invocation
https://bugs.freedesktop.org/show_bug.cgi?id=69203
Priority: medium
Bug ID: 69203
Assignee: nouveau at lists.freedesktop.org
Summary: Kernel 3.11 - Xorg hangs immediately after invocation
Severity: normal
Classification: Unclassified
OS: All
Reporter: alupu01 at gmail.com
Hardware: Other
2016 Oct 16
10
[PATCH 1/5] hwdefs: update nvc0_3d, add gm107_texture for new TIC format
These are copied directly from the mesa repository.
Signed-off-by: Ilia Mirkin <imirkin at alum.mit.edu>
---
src/hwdefs/gm107_texture.xml.h | 365 +++++++++++++++++
src/hwdefs/nvc0_3d.xml.h | 867 +++++++++++++++++++++++++----------------
2 files changed, 892 insertions(+), 340 deletions(-)
create mode 100644 src/hwdefs/gm107_texture.xml.h
diff --git
2016 Oct 27
11
[PATCH v2 0/7] Add Maxwell support
I believe I've addressed all the feedback from the first time around, and
also made fixes necessary for GM20x based on testing results. I believe
now it should actually work for all GM10x and GM20x. Further, GP10x should
be very easy to add, but without someone to actually test I didn't want to
claim support for it.
Ilia Mirkin (7):
exa: add GM10x acceleration support
hwdefs: update
2010 Dec 23
2
upsd crashes with a "broken pipe" error
In /var/log/syslog
Dec 23 13:04:50 ************** upsmon[2010]: Poll UPS
[rack1ups at localhost] failed - Write error: Broken pipe
After this, there is no longer a upsd daemon running.
Error messages follow:
Dec 23 13:04:50 ************** upsmon[2010]: Communications with UPS
rack1ups at localhost lost
...
Dec 23 13:04:55 ************** upsmon[2010]: UPS [rack1ups at localhost]:
connect