Displaying 3 results from an estimated 3 matches for "0b110011".
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0b11001
2008 Sep 15
1
[LLVMdev] Prevent a intrinsic to be reordered?
...The lower instruction (in MIPS):
class SORUI<bits<6> op, dag outs, dag ins, string asmstr, list<dag> pattern,
InstrItinClass itin>: FI<op, outs, ins, asmstr, pattern, itin>
{
let isBarrier = 1; // or call, hassideefects, ..., nothing work
}
def SORU_SRE: SORUI<0b110011, (outs), (ins uimm16:$imm), "sre $imm",
[(int_soru_sre imm:$imm)], IISoru>;
(With IISoru I made all the possible changes: a lot of cycles or none with
all the functional units or none)
And an example:
tail call void @llvm.soru.sre( i32 5 )
mul i32 %b, %a...
2008 Sep 14
0
[LLVMdev] Prevent a intrinsic to be reordered?
Hello, Julio
> These later things are ignored, I don't know if when the intrinsic is
> lowered, then it doesn't matter (or perhaps the reorder is made
> before).
What is the description of the instruction you're lowering intrinsic
into? Have you looked for the instruction flags defined in Target.td
file? You instruction should definitely have "isBarrier" flag set.
2008 Sep 14
3
[LLVMdev] Prevent a intrinsic to be reordered?
Hello, I have an intrinsic that matches to a asm instruction directly. This
intrinsic starts a coprocessor that can do anything.
If I put another instruction next to it (a multiplication for example), the
"llc" reorders and puts the intrinsic after the multiplication.
I have tried all:
- Setting the instruction like if it takes 256 cycles or 0 cycles.
- Setting the instruction with