Displaying 4 results from an estimated 4 matches for "0b1000".
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0.1000
2012 Sep 12
2
[LLVMdev] [PATCH][Review request] tablegen: extend list fields
...in a let statement or
placing a '"+" in front of a superclass:
- Example 1:
def D0 : C1 {
let Predicates += [P2]; // Append P2 to C1's Predicates
}
- Example 2:
def D0 : C1, +AddP1;
Using a real example, MOVi16 (in ARMInstrInfo.td) which is defined as
def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
DPFrm, IIC_iMOVi,
"movw", "\t$Rd, $imm",
[(set GPR:$Rd, imm0_65535:$imm)]>,
Requires<[IsARM, HasV6T2]>, UnaryDP {
can be rewritten to this:
class PredHasV...
2012 Sep 12
0
[LLVMdev] [llvm-commits] [PATCH][Review request] tablegen: extend list fields
...perclass:
>
> - Example 1:
>
> def D0 : C1 {
> let Predicates += [P2]; // Append P2 to C1's Predicates
> }
>
> - Example 2:
>
> def D0 : C1, +AddP1;
>
>
> Using a real example, MOVi16 (in ARMInstrInfo.td) which is defined as
>
> def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
> DPFrm, IIC_iMOVi,
> "movw", "\t$Rd, $imm",
> [(set GPR:$Rd, imm0_65535:$imm)]>,
> Requires<[IsARM, HasV6T2]>, UnaryDP {
>
>
> can be r...
2012 Sep 14
1
[LLVMdev] [llvm-commits] [PATCH][Review request] tablegen: extend list fields
...{
> > let Predicates += [P2]; // Append P2 to C1's Predicates
> > }
> >
> > - Example 2:
> >
> > def D0 : C1, +AddP1;
> >
> >
> > Using a real example, MOVi16 (in ARMInstrInfo.td) which is defined as
> >
> > def MOVi16 : AI1<0b1000, (outs GPR:$Rd), (ins imm0_65535_expr:$imm),
> > DPFrm, IIC_iMOVi,
> > "movw", "\t$Rd, $imm",
> > [(set GPR:$Rd, imm0_65535:$imm)]>,
> > Requires<[IsARM, HasV6T2]>, UnaryDP {
>...
2012 Jan 18
1
[LLVMdev] Pattern matching in a SelectionDAG
...g LLVM's retargetable code
generator, and I'm confused about how the SelectionDAG works. Let me give
you an example from the SPARC backend (as this is what is often mentioned
in the documentation). This is how the "branch always" instruction is
defined:
def BA : BranchSP<0b1000, (ins brtarget:$dst),
"ba $dst",
[(br bb:$dst)]>;
The pattern that is to be matched is simply (br bb: $dst). Based on this, I
would have expected the pattern for an add instruction to look somehow like
this: (add IntRegs:$b, IntRegs:$c). B...