Displaying 2 results from an estimated 2 matches for "0b011000".
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00011000
2012 Oct 15
2
[LLVMdev] Alternate instruction encoding for subtargets
...ew instructions which are not important at the moment, the
KCPSM6 cpu has different instruction opcodes. Semantically the
instructions are the same, hence I'd like to keep all the lowering and
pattern matching stuff unmodified
For example, the ADD sX, sY instruction in KCPSM3 is:
Inst{17-12} = 0b011000;
Inst{11-8} = sx;
Inst{7-4} = sy;
Inst{3-0} = 0;
While in KCPSM6 the same instruction is encoded:
Inst{17-12} = 0b010000;
Inst{11-8} = sx;
Inst{7-4} = sy;
Inst{3-0} = 0;
They even mostly kept the instruction formats!
Can I tell tablegen to have two encodings and switch between them
using a predic...
2011 Jul 03
0
[LLVMdev] DLX backend
...;, 0b001100, and>;
defm OR : RegisterImmediateFormat<"or", 0b001101, or>;
defm XOR : RegisterImmediateFormat<"xor", 0b001110, xor>;
// conditional instructions
/* ??? whats the format for the SDNode I need?
defm SEQ : RegisterImmediateFormat<"seq", 0b011000, icmp eq i32>;
defm SNE : RegisterImmediateFormat<"sne", 0b011001, icmp ne i32>;
defm SGE : RegisterImmediateFormat<"sge", 0b011101, icmp uge i32>;
defm SGT : RegisterImmediateFormat<"sgt", 0b011011, icmp ugt i32>;
defm SLE : RegisterImmediateForma...