search for: 0b000010

...EncoderMethod = "getMemEncoding"; } def addr : ComplexPattern<i32, 2, "SelectAddr", [frameindex], [SDNPWantParent]>; def LDRAM : FG1<0b000001, (outs GPRegs:$dst), (ins mem:$src), "ldram $dst,$src", [(set GPRegs:$dst, (load addr:$src))]>; def STRAM : FG1<0b000010, (outs), (ins GPRegs:$src, mem:$dst), "stram $dst,$src", [(store GPRegs:$src, addr:$dst)]>; def ADD : FG2<0b000000, (outs GPRegs:$dst), (ins GPRegs:$src1, GPRegs:$src2), "add $dst,$src1,$src2", [(set GPRegs:$dst, (add GPRegs:$src1, GPRegs:$src2))]>; Error Message: LDRA...

...2imm:$c), !strconcat(OpcStr, " $b, $c, $dst"), [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; } which allows it to use instructions like: defm AND : F3_12<"and" , 0b000001, and>; defm OR : F3_12<"or" , 0b000010, or>; defm XOR : F3_12<"xor" , 0b000011, xor>; defm SLL : F3_12<"sll" , 0b100101, shl>; defm SRL : F3_12<"srl" , 0b100110, srl>; defm SRA : F3_12<"sra" , 0b100111, sra>; defm ADD : F3_12<"add" , 0b00...

Hi, I'm trying to implement a new backend for an embedded CISC processor. Therefore I thought that it makes sense to take X86 target as a basis, to save some time. But when I look into the X86InstrInfo.td, I have a very strong feeling that it is one of the most complex instruction set descriptions compared to other targets. I can imagine that this is due to the complexity of X86's

...cat(OpcStr, " $b, $c, $dst"), > [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>; > } > > which allows it to use instructions like: > > defm AND : F3_12<"and" , 0b000001, and>; > defm OR : F3_12<"or" , 0b000010, or>; > defm XOR : F3_12<"xor" , 0b000011, xor>; > defm SLL : F3_12<"sll" , 0b100101, shl>; > defm SRL : F3_12<"srl" , 0b100110, srl>; > defm SRA : F3_12<"sra" , 0b100111, sra>; > defm ADD : F3_12&l...