Displaying 12 results from an estimated 12 matches for "0b000000".
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2008 Jul 03
1
Sins of Solar Empire: crash
...00:00 0
> 09c80000-09d80000 ---p 09c80000 00:00 0
> 09d80000-0a2b0000 rwxp 09d80000 00:00 0
> 0a2b0000-0a390000 ---p 0a2b0000 00:00 0
> 0a390000-0a8b0000 rwxp 0a390000 00:00 0
> 0a8b0000-0a9c0000 rwxp 0a8b0000 00:00 0
> 0a9c0000-0aad0000 rwxp 0a9c0000 00:00 0
> 0aad0000-0b000000 rwxp 0aad0000 00:00 0
> 0b000000-0b060000 ---p 0b000000 00:00 0
> 0b060000-0d030000 rwxp 0b060000 00:00 0
> 0d030000-0d080000 ---p 0d030000 00:00 0
> 0d080000-0f700000 rwxp 0d080000 00:00 0
> 0f700000-0f920000 rwxp 0f700000 00:00 0
> 0f920000-0fa30000 rwxp 0f920000 00:00 0...
2007 Oct 21
1
[LLVMdev] Adding address registers to back-end
...isters are elements in the
>> register sets IntRegs and AddrRegs.
>
> /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
> multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
> ....
> }
>
> defm ADD : F3_12<"add", 0b000000, add>;
>
> Instruction ADD output register class is IntRegs. It does not match
> AddrRegs. That's why you are getting the assertion.
The address register set AddrRegs is a subset of IntRegs. Do you
compare the register set identifiers instead of the register itself
and if it...
2007 Oct 19
0
[LLVMdev] Adding address registers to back-end
...egs:
$c))]>;
def ri : F3_2<2, Op3Val,
(outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
!strconcat(OpcStr, " $b, $c, $dst"),
[(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
}
defm ADD : F3_12<"add", 0b000000, add>;
Instruction ADD output register class is IntRegs. It does not match
AddrRegs. That's why you are getting the assertion.
What you need is to define a parallel set of instructions that target
the address register class. Then you can tell the instruction
selector to select to the...
2007 Oct 19
2
[LLVMdev] Adding address registers to back-end
Hi!
I'm writing a new back-end for a new architecture. First, I'll do
some "tests" with an existing back-end (I chose the Sparc back-end).
My architecture has special address-registers and I want to add such
new address-registers to my Sparc back-end.
1) I defined a new register call AddrRegs
2) I registered the class AddrRegs (addRegisterClass(MVT::iPTR, .. ))
3) I
2014 Jun 07
3
[LLVMdev] Load/Store Instruction Error
...arent]>;
def LDRAM : FG1<0b000001, (outs GPRegs:$dst), (ins mem:$src), "ldram
$dst,$src", [(set GPRegs:$dst, (load addr:$src))]>;
def STRAM : FG1<0b000010, (outs), (ins GPRegs:$src, mem:$dst), "stram
$dst,$src", [(store GPRegs:$src, addr:$dst)]>;
def ADD : FG2<0b000000, (outs GPRegs:$dst), (ins GPRegs:$src1,
GPRegs:$src2), "add $dst,$src1,$src2", [(set GPRegs:$dst, (add
GPRegs:$src1, GPRegs:$src2))]>;
Error Message:
LDRAM: (set GPRegs:{i32:f32}:$dst, (ld:{i32:f32}
addr:iPTR:$src)<<P:Predicate_unindexedload>><<P:Predicate_load>&g...
2013 May 27
0
[LLVMdev] Problem with LEA_ADDri
Hi
The construct in sparc
def LEA_ADDri : F3_2<2, 0b000000,
(outs IntRegs:$dst), (ins MEMri:$addr),
"add ${addr:arith}, $dst",
[(set IntRegs:$dst, ADDRri:$addr)]>;
generate instruction like : add %fp, -20, %l1
in my port it generate like : addi %fp, -20, %r2
But the problem is that...
2006 Oct 02
0
[LLVMdev] Instruction descriptions question
...0010, or>;
defm XOR : F3_12<"xor" , 0b000011, xor>;
defm SLL : F3_12<"sll" , 0b100101, shl>;
defm SRL : F3_12<"srl" , 0b100110, srl>;
defm SRA : F3_12<"sra" , 0b100111, sra>;
defm ADD : F3_12<"add" , 0b000000, add>;
defm ADDCC : F3_12<"addcc", 0b010000, addc>;
defm ADDX : F3_12<"addx" , 0b001000, adde>;
defm SUB : F3_12<"sub" , 0b000100, sub>;
defm SUBX : F3_12<"subx" , 0b001100, sube>;
defm SUBCC : F3_12<"subcc",...
2006 Nov 17
1
[LLVMdev] LLVM backend Issues
Here's the PDF version.
On Thu, 2006-11-16 at 20:50 -0800, Chris Lattner wrote:
> On Fri, 17 Nov 2006, [ks_c_5601-1987] "̽" wrote:
> >
> > The attached document contains the present issues I met while developing
> > a LLVM backend emits text assembly code for a new architecture. Most of
> > them are problems should be resolved.
> > I sincerely ask
2006 Apr 10
1
Where is the documentation for IFB ?
Hi all,
Can you tell me where is the documentation for the new IFB (implemented
in kernels > 2.6.16).
Thanks in advance!
Nikolay
2006 Oct 01
2
[LLVMdev] Instruction descriptions question
Hi,
I'm trying to implement a new backend for an embedded CISC processor.
Therefore I thought that it makes sense to take X86 target as a basis,
to save some time.
But when I look into the X86InstrInfo.td, I have a very strong feeling
that it is one of the most complex instruction set descriptions
compared to other targets. I can imagine that this is due to the
complexity of X86's
2006 Oct 02
2
[LLVMdev] Instruction descriptions question
...OR : F3_12<"xor" , 0b000011, xor>;
> defm SLL : F3_12<"sll" , 0b100101, shl>;
> defm SRL : F3_12<"srl" , 0b100110, srl>;
> defm SRA : F3_12<"sra" , 0b100111, sra>;
> defm ADD : F3_12<"add" , 0b000000, add>;
> defm ADDCC : F3_12<"addcc", 0b010000, addc>;
> defm ADDX : F3_12<"addx" , 0b001000, adde>;
> defm SUB : F3_12<"sub" , 0b000100, sub>;
> defm SUBX : F3_12<"subx" , 0b001100, sube>;
> defm SUBCC : F3_...
2004 Aug 08
14
Problems booting 2.6.7 Dom0 with 3ware Controllers
I tried to install and boot a 2.6.7 Dom0 xenLinux Kernel on an
SMP (Dual-Xeon) Machine with 2 3-ware Controllers installed
(1 4-channel Controler and 1 8-channel Controler, both Parallel ATA)
and no other HDs present (except the ones connected to the
3ware controlers, of course).
First of all I got a compilation error after activating the SMP option
in the kernel config.
After deactivating the