Nouveau - Nov 2025 - [PATCH 03/11] gpu: nova-core: support header parsing on Turing/GA100

On 11/24/25 3:47 PM, Timur Tabi wrote:
> On Wed, 2025-11-19 at 15:10 -0500, Joel Fernandes wrote:
>> ???????? sec2_falcon.reset(bar)?;
>> -??????? if chipset > Chipset::GA100 {
>> +??????? if booter_loader.flags() == BooterFlags::Secure {
>> ???????????? sec2_falcon.dma_load(bar, &booter_loader)?;
>> ???????? } else {
>> ???????????? sec2_falcon.pio_load(bar, &booter_loader, None)?;
> 
> The problem with this is that it conflates (Non-)Secure IMEM with using
PIO/DMA.  I haven't looked
> at GA100 yet, but it's just coincidence that platforms that have
Non-Secure IMEM sections also don't
> have (functioning) DMA hardware.
> 
Hopper/Blackwell+ use PIO too. So the conflating could be a real
concern.

thanks,
-- 
John Hubbard

On Tue Nov 25, 2025 at 8:55 AM JST, John Hubbard wrote:
> On 11/24/25 3:47 PM, Timur Tabi wrote:
>> On Wed, 2025-11-19 at 15:10 -0500, Joel Fernandes wrote:
>>> ???????? sec2_falcon.reset(bar)?;
>>> -??????? if chipset > Chipset::GA100 {
>>> +??????? if booter_loader.flags() == BooterFlags::Secure {
>>> ???????????? sec2_falcon.dma_load(bar, &booter_loader)?;
>>> ???????? } else {
>>> ???????????? sec2_falcon.pio_load(bar, &booter_loader, None)?;
>> 
>> The problem with this is that it conflates (Non-)Secure IMEM with using
PIO/DMA.  I haven't looked
>> at GA100 yet, but it's just coincidence that platforms that have
Non-Secure IMEM sections also don't
>> have (functioning) DMA hardware.
>> 
>
> Hopper/Blackwell+ use PIO too. So the conflating could be a real
> concern.
Ok, so we really want to have this handled by the falcon HAL as Timur
suggested.