llvm dev - Oct 2021 - Question about RISCV gp-relaxtion

Maybe the LLD doesn't support linker relaxtion (It is difficult to
implement).
(Correct me if I'm wrong)



I want to implement lwgp, 17-bit/128KB gp-offset.
(https://github.com/riscv/riscv-code-size-reduction/blob/after_v0.50.1_dev/ISA%20proposals/Huawei/Zce_spec.adoc#lwgp_semantics)

Eg:  lui a0, %hi(sym); load/store a1, %lo(sym)(a0) -> lwgp/swgp a1,
gp_offset(gp)




question: 

1. Do I have to support linker relaxtion if I want to implement lwgp?   

2. Is there any other way to solve the problem？ assmembler? 


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At 2021-10-15 15:01:30, "liao" <liaochunyu126 at 126.com> wrote:

Maybe the LLD doesn't support linker relaxtion (It is difficult to
implement).
(Correct me if I'm wrong)



I want to implement lwgp, 17-bit/128KB gp-offset.
(https://github.com/riscv/riscv-code-size-reduction/blob/after_v0.50.1_dev/ISA%20proposals/Huawei/Zce_spec.adoc#lwgp_semantics)

Eg:  lui a0, %hi(sym); load/store a1, %lo(sym)(a0) -> lwgp/swgp a1,
gp_offset(gp)




question: 

1. Do I have to support linker relaxtion if I want to implement lwgp?   

2. Is there any other way to solve the problem？ assmembler? 







 
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