As far as I have understood it, register banks gives the ability of analyzing
and making a partial register assignment before selecting the instructions. In
SelectionISel, instructions are selecting without taking any consideration to
register classes, which could potentially result in code with excess copying
between register classes.
This problem can be indeed resolved by adding more abstract forms of register
banks; this is actually what we currently do for our target. Register banks
just gives a uniform way of handling it.
Cheers,
Gabriel
-----Original Message-----
From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Paul C.
Anagnostopoulos via llvm-dev
Sent: den 19 december 2020 17:30
To: llvm-dev at lists.llvm.org
Subject: [llvm-dev] Register banks
What do register banks do that could not have been done by enhancing register
classes? Is it a matter of separation of concerns?
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