llvm dev - Oct 2020 - RISC-V Custom Instruction Parsing Features

Recently I have tried to introduce the RISC-V Platform in my workplace, 
and had to make some custom instructions within RISC-V ISA. When 
planning to set some custom value in ISA for our custom functions in our 
CPU, GNU toolchain offers .insn features to replace the opcodes with our 
value in it.

So I just wonder does clang/llvm support those features for developers 
to enable building the source/assembly with their own custom instruction 
value in it?

We're working on it, and know it is missing functionality. I believe a
colleague of mine has started work on a patch but it is not complete yet.

Sam
> On 2 Oct 2020, at 4:52 pm, Caool via llvm-dev <llvm-dev at
lists.llvm.org> wrote:
> 
> Recently I have tried to introduce the RISC-V Platform in my workplace, and
had to make some custom instructions within RISC-V ISA. When planning to set
some custom value in ISA for our custom functions in our CPU, GNU toolchain
offers .insn features to replace the opcodes with our value in it.
> 
> So I just wonder does clang/llvm support those features for developers to
enable building the source/assembly with their own custom instruction value in
it?
> 
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
--
Sam Elliott
Software Team Lead
Senior Software Developer - LLVM and OpenTitan
lowRISC CIC

-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20201029/a22cc2f4/attachment.html>