Thomas Preud'homme via llvm-dev
2020-Jun-16 16:36 UTC
[llvm-dev] How to mark intrinsic a barrier
Hi, I'm trying to compile a code similar to the ARM testcase attached but for a different target where a piece of floating-point code must execute without interrupt being raised in case of underflow/overflow or similar cases. However both the SelectionDAG scheduler and Machine Instruction scheduler move the FPSCR setting instruction around. Case in point, in my testing this testcase gets compiled as: vmrs r0, fpscr vmul s0, s0, s1 bic r1, r0, #40704 vmsr fpscr, r1 vmsr fpscr, r0 bx lr I've found that I could use isSchedulingBoundary to mark vmsr as a barrier but how about the SelectionDAG scheduler? Best regards, Thomas -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20200616/84130ee9/attachment.html> -------------- next part -------------- A non-text attachment was scrubbed... Name: set_fpscr_fp_ops_arm.cpp Type: text/x-c++src Size: 325 bytes Desc: set_fpscr_fp_ops_arm.cpp URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20200616/84130ee9/attachment.cpp>