llvm dev - Jun 2019 - union of register classes

Suppose I have a target system with two different register classes which hold
different values,  let us refer to them as Prc and Src, and individual elements
P0,P1,… and S0,S1… respectively

Now I have an instruction which has a field that takes either a Prc or an Src.

If I create a third register class which combines all of the individual
registers and has both types, then I get an error such as

error: Value #0 of OperandWithDefaultOps  ‘’FOO” doesn't have a concrete
type!

Where effectively I had

               def Prc : registerclass<’”ns”, [Type1], 8 (add P0, … )>

               def Src : registerclass<’”ns”, [Type2], 8 (add S0, … )>

               def PSrc : registerclass<”ns”, [Type1, Type2], 8, (add P0….,
S0…)>

               def Pop : RegisterOperand<Prc> { }

               def FOO : OperandWithDefaults<Type1, (ops P0)>

What guidance or examples are there for approaching this kind of problem?

Thanks

david

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> On Jun 27, 2019, at 08:54, David Callahan via llvm-dev <llvm-dev at
lists.llvm.org> wrote:
> 
>                def PSrc : registerclass<”ns”, [Type1, Type2], 8, (add
P0…., S0…)>
I think this should be specified as (add PSrc, Src), rather than adding the same
register elements to each
>                def Pop : RegisterOperand<Prc> { }
>                def FOO : OperandWithDefaults<Type1, (ops P0)>
> 
II don’t think tablegen is smart enough to infer the type here. I think this
should work if you explicitly list (ops (Type1 P0)), but I also haven’t seen
OperandWithDefaults used with something that isn’t an immediate.

-Matt
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