Hi All, One thing I believe also bothers someone else. Say we have the following code snippet: bits<32> insnEncoding; let insnEncoding{15-12} = 0b0100; Can we write the let expression with range list like this, with the same meaning? let insnEncoding{12-15} = 0b0100; I take a look on TGParser::ParseRangePiece (lib/TableGen/TGParser.cpp), seems the answer is YES. Can anyone confirm this? Thanks. Regards, chenwj -- Wei-Ren Chen (陳韋任) Homepage: https://people.cs.nctu.edu.tw/~chenwj -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20170415/617c5f27/attachment.html>
Okay, a little experiment shows the order matters. $ cat bits_4_0.td def basic_bits { bits<10> zz; let zz{4-0} = 0b11001; } $ llvm-tblgen bits_4_0.td def basic_bits { bits<10> zz = { ?, ?, ?, ?, ?, 1, 1, 0, 0, 1 }; string NAME = ?; } $ cat bits_0_4.td def basic_bits { bits<10> zz; let zz{0-4} = 0b11001; } $ llvm-tblgen bits_4_0.td def basic_bits { bits<10> zz = { ?, ?, ?, ?, ?, 1, 0, 0, 1, 1 }; string NAME = ?; } 2017-04-15 23:55 GMT+08:00 陳韋任 <chenwj.cs97g at g2.nctu.edu.tw>:> Hi All, > > One thing I believe also bothers someone else. Say we have the following > code snippet: > > bits<32> insnEncoding; > let insnEncoding{15-12} = 0b0100; > > Can we write the let expression with range list like this, with the same > meaning? > > let insnEncoding{12-15} = 0b0100; > > I take a look on TGParser::ParseRangePiece (lib/TableGen/TGParser.cpp), > seems the > answer is YES. Can anyone confirm this? > > Thanks. > > Regards, > chenwj > > -- > Wei-Ren Chen (陳韋任) > Homepage: https://people.cs.nctu.edu.tw/~chenwj-- Wei-Ren Chen (陳韋任) Homepage: https://people.cs.nctu.edu.tw/~chenwj
On 15 April 2017 at 19:52, 陳韋任 via llvm-dev <llvm-dev at lists.llvm.org> wrote:> Okay, a little experiment shows the order matters.Interesting, thanks for reporting back. Personally I find it pretty scary that we support the second form at all. It's mixing two different endiannesses with no real indication of which one will win. Tim.
Maybe Matching Threads
- About TableGen RangeList
- [LLVMdev] troubles with llvm-gcc 4.0 and APFloat on X86_64
- [LLVMdev] RegisterClass constraints in TableGen
- [tablegen] table readability / performance
- [LLVMdev] cross compiling for arm-softfloat-linux-gnu (was troubles with llvm-gcc 4.0 and APFloat on X86_64)