llvm dev - Mar 2017 - Using llc -disablg-cgp to fix instruction selection (store) error

Hello.
     I want to report a bug I encountered and the quick fix I found.
     Basically I was getting the following rather strange instruction selection
error for
a program using vector LLVM IR instructions when giving llc -O1 (but not for
-O0):
         ISEL: Starting pattern match on root node: t8965: ch =
store<ST256[FixedStack0]>
t0, t1068, FrameIndex:i64<0>, undef:i64
           Initial Opcode index to 157
           Skipped scope entry (due to false predicate) at index 162, continuing
at 236
           Match failed at index 241
           Continuing at 263
         LLVM ERROR: Cannot select: t8965: ch = store<ST256[FixedStack0]>
t0, t1068,
FrameIndex:i64<0>, undef:i64
           t1068: v128i16 = add t9412, t9540
             t9412: v128i16 = insert_vector_elt t9411, t5182,
Constant:i64<127>
               t9411: v128i16 = insert_vector_elt t9410, t5184,
Constant:i64<126>
                 t9410: v128i16 = insert_vector_elt t9409, t5186,
Constant:i64<125>
                   t9409: v128i16 = insert_vector_elt t9408, t5188,
Constant:i64<124>
                     t9408: v128i16 = insert_vector_elt t9407, t5190,
Constant:i64<123>
                       t9407: v128i16 = insert_vector_elt t9406, t5192,
Constant:i64<122>
                         t9406: v128i16 = insert_vector_elt t9405, t5194,
Constant:i64<121>
                           t9405: v128i16 = insert_vector_elt t9404, t5196,
Constant:i64<120>

     Note: I saw also that my vector loads and stores (gathers and scatters, to
be more
exact) are treated differently: LD256 is broken into several LD2 instructions;
ST256 has
FrameIndex / FixedStack0 attributes now (for llc -O0 I think it does not).

     I had the inspiration to examine the standard output of llc around a
message "CGP:
Found ...", which was something new from llc -O0. This message is generated
by method
CodeGenPrepare::optimizeMemoryInst(), which "is used to optimize both
load/store and
inline asms with memory operands."

     So I gave llc -O1 -disable-cgp to Disable Codegen Prepare and I got NO more
error at
llc -O1.

     Any comment on this solved issue is appreciated.

   Best regards,
     Alex

On 3/8/2017 12:32 AM, Alex Susu via llvm-dev wrote:
>   Hello.
>     I want to report a bug I encountered and the quick fix I found.
>     Basically I was getting the following rather strange instruction 
> selection error for a program using vector LLVM IR instructions when 
> giving llc -O1 (but not for -O0):
>         ISEL: Starting pattern match on root node: t8965: ch = 
> store<ST256[FixedStack0]> t0, t1068, FrameIndex:i64<0>,
undef:i64
>           Initial Opcode index to 157
>           Skipped scope entry (due to false predicate) at index 162, 
> continuing at 236
>           Match failed at index 241
>           Continuing at 263
>         LLVM ERROR: Cannot select: t8965: ch = 
> store<ST256[FixedStack0]> t0, t1068, FrameIndex:i64<0>,
undef:i64
"Cannot select" means that you haven't defined a pattern which
matches
the node in question.  In this case, it means you don't have a pattern 
for a v128i16 store instruction.
>           t1068: v128i16 = add t9412, t9540
>             t9412: v128i16 = insert_vector_elt t9411, t5182, 
> Constant:i64<127>
>               t9411: v128i16 = insert_vector_elt t9410, t5184, 
> Constant:i64<126>
>                 t9410: v128i16 = insert_vector_elt t9409, t5186, 
> Constant:i64<125>
>                   t9409: v128i16 = insert_vector_elt t9408, t5188, 
> Constant:i64<124>
>                     t9408: v128i16 = insert_vector_elt t9407, t5190, 
> Constant:i64<123>
>                       t9407: v128i16 = insert_vector_elt t9406, t5192, 
> Constant:i64<122>
>                         t9406: v128i16 = insert_vector_elt t9405, 
> t5194, Constant:i64<121>
>                           t9405: v128i16 = insert_vector_elt t9404, 
> t5196, Constant:i64<120>
>
>     Note: I saw also that my vector loads and stores (gathers and 
> scatters, to be more exact) are treated differently: LD256 is broken 
> into several LD2 instructions; ST256 has FrameIndex / FixedStack0 
> attributes now (for llc -O0 I think it does not).
>
>     I had the inspiration to examine the standard output of llc around 
> a message "CGP: Found ...", which was something new from llc -O0.
This
> message is generated by method CodeGenPrepare::optimizeMemoryInst(), 
> which "is used to optimize both load/store and inline asms with memory
> operands."
>
>     So I gave llc -O1 -disable-cgp to Disable Codegen Prepare and I 
> got NO more error at llc -O1.
>
>     Any comment on this solved issue is appreciated.
You're probably papering over the bug; codegenprepare is just a bunch of 
miscellaneous late IR optimizations.

-Eli

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