Our target uses write-only registers to split a 3-operands operation into a write to special-register instruction and a 2-operands instruction for this operation: res := op(src1,src2,src3) becomes: MV specialreg, src3 OP res, src1, src2 <implicit read of specialreg> I'm used to put all source operands with their register-classes in the pattern ins-dags and use them in the pattern: "def: .... (ins GPR:$src1, GPR:$src2, SPECIALREG:$src3) ..." This works as expected: an instruction to write src3 to the specialreg (by register write instruction) and the instruction for the operation are emitted. But sooner or later the register-allocator uses this write-only specialreg to move data around, which is illegal. At the moment I solve this by a) reserving this write-only specialreg and b) having an explicit specialreg-write operation and the instruction OP with an implicit DEF and USE for specialreg respectively. Is there a chance to save my first implementation? It's more elegant and generates more efficient code if the same value is written multiple times to specialreg. Thanks, Boris