Ryan Taylor via llvm-dev
2016-Oct-17 21:47 UTC
[llvm-dev] Generate Register Indirect mode instruction
I was under the impression his answer was correct from your reply, no? On Oct 17, 2016 17:45, "Alex Bradley via llvm-dev" <llvm-dev at lists.llvm.org> wrote:> Gentle Ping !! > > I would appreciate any help on this. I want to generate following as > described by Krzysztof : > > %v1 = load i32, i32* %a > %v2 = load i32, i32* %b > %v3 = add i32 %v1, %v2 > store i32 %v3, i32* %c > > maps to (using invented mnemonics): > > ASSIGN R0, %a > ASSIGN R1, %b > ASSIGN R2, %c > ADD *R2, *R0, *R1 > > Thanks. > > Regards, > Alex > > On 14 Oct 2016 1:00 p.m., "Alex Bradley" <alexbradley.bqc at gmail.com> > wrote: > >> >> > If I understand correctly: >> > >> > %v1 = load i32, i32* %a >> > %v2 = load i32, i32* %b >> > %v3 = add i32 %v1, %v2 >> > store i32 %v3, i32* %c >> > >> > maps to (using invented mnemonics): >> > >> > ASSIGN R0, %a >> > ASSIGN R1, %b >> > ASSIGN R2, %c >> > ADD *R2, *R0, *R1 >> > >> > I.e. pattern >> > (store %c, (add (load %a), (load %b))) >> > becomes >> > (ADD (ASSIGN R2, %c), (ASSIGN R0, %a), (ASSIGN R1, %b)) >> > >> >> Yes. Exactly. >> >> Regards, >> Alex >> > > _______________________________________________ > LLVM Developers mailing list > llvm-dev at lists.llvm.org > http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev > >-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20161017/68d9b266/attachment.html>
Alex Bradley via llvm-dev
2016-Oct-17 21:57 UTC
[llvm-dev] Generate Register Indirect mode instruction
Hi Ryan, Yes. But I am unable to think where in the code will it go? Will it be in a .td file where I define a pattern and during InstructionSelection, the pattern matches and emits the code automatically? Or do I need to write a pass for it? I am new to llvm backend and trying to figure out things. Any help will be a great deal. Thanks. Regards, Alex On 18 Oct 2016 3:17 a.m., "Ryan Taylor" <ryta1203 at gmail.com> wrote:> I was under the impression his answer was correct from your reply, no? > > On Oct 17, 2016 17:45, "Alex Bradley via llvm-dev" < > llvm-dev at lists.llvm.org> wrote: > >> Gentle Ping !! >> >> I would appreciate any help on this. I want to generate following as >> described by Krzysztof : >> >> %v1 = load i32, i32* %a >> %v2 = load i32, i32* %b >> %v3 = add i32 %v1, %v2 >> store i32 %v3, i32* %c >> >> maps to (using invented mnemonics): >> >> ASSIGN R0, %a >> ASSIGN R1, %b >> ASSIGN R2, %c >> ADD *R2, *R0, *R1 >> >> Thanks. >> >> Regards, >> Alex >> >> On 14 Oct 2016 1:00 p.m., "Alex Bradley" <alexbradley.bqc at gmail.com> >> wrote: >> >>> >>> > If I understand correctly: >>> > >>> > %v1 = load i32, i32* %a >>> > %v2 = load i32, i32* %b >>> > %v3 = add i32 %v1, %v2 >>> > store i32 %v3, i32* %c >>> > >>> > maps to (using invented mnemonics): >>> > >>> > ASSIGN R0, %a >>> > ASSIGN R1, %b >>> > ASSIGN R2, %c >>> > ADD *R2, *R0, *R1 >>> > >>> > I.e. pattern >>> > (store %c, (add (load %a), (load %b))) >>> > becomes >>> > (ADD (ASSIGN R2, %c), (ASSIGN R0, %a), (ASSIGN R1, %b)) >>> > >>> >>> Yes. Exactly. >>> >>> Regards, >>> Alex >>> >> >> _______________________________________________ >> LLVM Developers mailing list >> llvm-dev at lists.llvm.org >> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >> >>-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20161017/27392e60/attachment.html>
Ryan Taylor via llvm-dev
2016-Oct-17 22:08 UTC
[llvm-dev] Generate Register Indirect mode instruction
XXXInstrInfo.td (table gen instruction information where XXX is your target) Match automatically. On Oct 17, 2016 17:57, "Alex Bradley" <alexbradley.bqc at gmail.com> wrote:> Hi Ryan, > > Yes. But I am unable to think where in the code will it go? Will it be in > a .td file where I define a pattern and during InstructionSelection, the > pattern matches and emits the code automatically? Or do I need to write a > pass for it? > > I am new to llvm backend and trying to figure out things. Any help will be > a great deal. > > Thanks. > > Regards, > Alex > > On 18 Oct 2016 3:17 a.m., "Ryan Taylor" <ryta1203 at gmail.com> wrote: > >> I was under the impression his answer was correct from your reply, no? >> >> On Oct 17, 2016 17:45, "Alex Bradley via llvm-dev" < >> llvm-dev at lists.llvm.org> wrote: >> >>> Gentle Ping !! >>> >>> I would appreciate any help on this. I want to generate following as >>> described by Krzysztof : >>> >>> %v1 = load i32, i32* %a >>> %v2 = load i32, i32* %b >>> %v3 = add i32 %v1, %v2 >>> store i32 %v3, i32* %c >>> >>> maps to (using invented mnemonics): >>> >>> ASSIGN R0, %a >>> ASSIGN R1, %b >>> ASSIGN R2, %c >>> ADD *R2, *R0, *R1 >>> >>> Thanks. >>> >>> Regards, >>> Alex >>> >>> On 14 Oct 2016 1:00 p.m., "Alex Bradley" <alexbradley.bqc at gmail.com> >>> wrote: >>> >>>> >>>> > If I understand correctly: >>>> > >>>> > %v1 = load i32, i32* %a >>>> > %v2 = load i32, i32* %b >>>> > %v3 = add i32 %v1, %v2 >>>> > store i32 %v3, i32* %c >>>> > >>>> > maps to (using invented mnemonics): >>>> > >>>> > ASSIGN R0, %a >>>> > ASSIGN R1, %b >>>> > ASSIGN R2, %c >>>> > ADD *R2, *R0, *R1 >>>> > >>>> > I.e. pattern >>>> > (store %c, (add (load %a), (load %b))) >>>> > becomes >>>> > (ADD (ASSIGN R2, %c), (ASSIGN R0, %a), (ASSIGN R1, %b)) >>>> > >>>> >>>> Yes. Exactly. >>>> >>>> Regards, >>>> Alex >>>> >>> >>> _______________________________________________ >>> LLVM Developers mailing list >>> llvm-dev at lists.llvm.org >>> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev >>> >>>-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20161017/0f88c147/attachment.html>