llvm dev - Sep 2016 - how to allocate consecutive register?

Hi,

The gpu target  I am working on requires the 'value' and
'address' operands
of memory store instruction in consecutive register. Anybody has suggestion?

- Ruiling
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Hi Ruiling,

Make the store instruction takes only one operand, a tuple register.
You have examples of tuple registers in the ARM backend.

Cheers,
-Quentin
> On Sep 9, 2016, at 5:56 AM, Ruiling Song via llvm-dev <llvm-dev at
lists.llvm.org> wrote:
> 
> Hi,
> 
> The gpu target  I am working on requires the 'value' and
'address' operands of memory store instruction in consecutive register.
Anybody has suggestion?
> 
> - Ruiling
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev

There are other CPUs with similar restrictions. You could look at how they
handle it. An example which springs to mind is ARM A32 LDRD and STRD
(load/store two consecutive registers). I think some other architectures do
the same for operations which return two results, such as div/mod or
NxN->2N multiply.


On Fri, Sep 9, 2016 at 3:56 PM, Ruiling Song via llvm-dev <
llvm-dev at lists.llvm.org> wrote:
> Hi,
>
> The gpu target  I am working on requires the 'value' and
'address'
> operands of memory store instruction in consecutive register. Anybody has
> suggestion?
>
> - Ruiling
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>
>
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On 9 September 2016 at 21:19, Quentin Colombet via llvm-dev
<llvm-dev at lists.llvm.org> wrote:
> Make the store instruction takes only one operand, a tuple register.
> You have examples of tuple registers in the ARM backend.
The difficult bit will be if there are loads with the same property. I
don't think you can easily encode the fact that one half of a register
is read and the other written.

Tim.