llvm dev - Jan 2016 - [Intern Ad] Internship on high-level programming tools for FPGA at Xilinx

==================================================== OpenCL SYCL C++ compiler
and runtime for CPU & FPGA
====================================================
Internship on high-level programming tools for FPGA


Xilinx, the leading company specialized in FPGA, is looking for some
interns to work on C++-based high-level programming tools to ease FPGA
programming with improved productivity.

FPGA are reconfigurable MPSoC including CPU, GPU, reprogrammable logic
and various specific accelerators (video CODEC...) and I/O subsystems
(100 GE, PCI, memory buses...). This complexity makes them versatile
systems that can be used as accelerators but this also makes their use
difficult compared to simpler CPU-only environments.

Fortunately, at the same time there are various open standards for
heterogeneous computing, such as OpenCL or OpenMP 4.5, being developed
to ease the programming of accelerators. Xilinx is pushing these
standards as a way to simplify FPGA programming.

The Domain Specific Languages (DSL) are an interesting high-level
approach to simplify programming by specializing on the problems to be
solved. OpenCL SYCL is a DSL based on pure modern C++ to represent the
concepts used to program accelerators directly as C++ class without
any extension or compiler to avoid portability issues.

The goal of this internship is to develop a SYCL open source
environment targeted FPGA and CPU for emulation:

- a first part is to extend the runtime implentation
  https://github.com/amd/triSYCL based on OpenCL and OpenMP API;

- a second part is to adapt the open source compiler Clang/LLVM by
  adding an outliner to extract the code of the computational kernels
  and improve the compiler flow to generate the SPIR-V portable
  intermediate representation to address the existing Vivado HLS and
  SDAccel tools from Xilinx. Khronos provides open source components
  to deal with OpenCL C++ and SPIR-V to help in this task;

- the test infrastructure is to be extended at the same time with the
  development of some small applications;

- in parallel to the implementation, a prospective research to define
  the standards themselves will be done.

The positions are based in Dublin (Ireland) and suited typically for
master students, but of course other profiles can apply (PhD
students...).

The candidate will have the opportunity to get involved into advanced
technologies through the standardization committees of Khronos OpenCL
& SYCL, OpenMP and C++, and meet all the leading companies and
labortories behind these technologies.

The areas and subjects of the internship are:

- implementing parallel languages and run-times (OpenCL SYCL 2.2+
  https://www.khronos.org/sycl and OpenMP 4.5+ http://openmp.org );
- compilation (Clang/LLVM http://llvm.org/ and SPIR-V
  https://www.khronos.org/spir );
- FPGA & accelerators;
- C++1z, STL, Boost;
- DSL & DSeL;
- HPC & real-time applications and libraries;
- https://github.com/amd/triSYCL
- https://github.com/KhronosGroup/SyclParallelSTL
- open source software;
- git;
- Linux.

Gratification: 1500 €/month

Send applications and questions to Ronan.Keryell at Xilinx dot com.
-- 
  Ronan KERYELL
  Xilinx Research Labs, Dublin, Ireland