Hi everyone, I have an issue with the lowering of one of my bench. Here are the concert ".ll" part : call void %tmp10(i16* %tmp5, i16* %tmp6, i16 signext 64, i16 signext 8) #2 %tmp11 = call i32 @TH_StopTimer() #2 br label %bb20-L02 ... bb20-L02: ; preds = %bb18-L02, %.preheader %indvars.iv14 = phi i64 [ 0, %.preheader ], [ %indvars.iv.next15, %bb18-L02 ] %tmp21 = getelementptr inbounds [8 x i16]* %ad, i64 0, i64 %indvars.iv14 %tmp22 = load i16* %tmp21, align 2 %tmp23 = getelementptr inbounds [8 x i16]* @cor, i64 0, i64 %indvars.iv14 %tmp24 = load i16* %tmp23, align 2 %tmp25 = icmp eq i16 %tmp22, %tmp24 %indvars.iv.next15 = add nuw nsw i64 %indvars.iv14, 1 br i1 %tmp25, label %bb18-L02, label %bb26 When the call of @TH_StopTimer is lowered, I have this kind of code : ADJCALLSTACKDOWN ... CALL <ga:@TH_StopTimer>, %GRF0<imp-def,dead>, ... %vreg112<def> = MAKED 0; IR64:%vreg112 ADJCALLSTACKUP %GRF0<imp-def>, ... %vreg122<def> = COPY %GRF0; IR32:%vreg122 %vreg12<def> = COPY %vreg122; IR32:%vreg12,%vreg122 GOTO <BB#13> The return value of my call will be in the GRF0 register. But during the register allocation, as the GRF0 register is mark as dead in the CALL instruction, %vreg112 will be GRF0... I intended the MAKED instruction to be after the ADJCALLSTACKUP at least. Even after the COPYs in the best case. This MAKED instruction seems to come from the phi node of the bb20-L02 basic block. Does anyone already had a similar issue? Best Regards, Romaric