Ralph Campbell
2015-Feb-09 22:19 UTC
[LLVMdev] aarch64 status for generating SIMD instructions
So far, all I have tried is -O3 and with & without "-mcpu=cortex-a57". I'm new to LLVM so I'm not familiar with what optimization flags are available. I tried poking around in the LLVM documentation but haven't found a definitive list. The clang man page is skimpy on details. From: Arnaud A. de Grandmaison [mailto:arnaud.degrandmaison at arm.com] Sent: Monday, February 09, 2015 2:11 PM To: Ralph Campbell Cc: llvmdev at cs.uiuc.edu Subject: RE: aarch64 status for generating SIMD instructions Which compiler flags have you been using ? There is definitely support for AArch64's SIMD instructions, but their use depends on what the vectorizers can do with your code. From: llvmdev-bounces at cs.uiuc.edu<mailto:llvmdev-bounces at cs.uiuc.edu> [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Ralph Campbell Sent: 09 February 2015 22:30 To: llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu> Subject: [LLVMdev] aarch64 status for generating SIMD instructions I'm using Fedora 22 and gcc 4.9.2 to run llvm 3.5.1 on an ARM Juno reference box (cortex A53 & A57). I tried compiling some simple functions like dot product and axpy() into assembly to see if any of the SIMD instructions were generated (they weren't). Perhaps I'm missing some compiler flag to enable it. Does anyone know what the status is for aarch64 generating SIMD instructions? Anyone coordinating or leading this effort? (if there is one) -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150209/9fd7a80a/attachment.html>
Arnaud A. de Grandmaison
2015-Feb-09 22:54 UTC
[LLVMdev] aarch64 status for generating SIMD instructions
You can try something along the lines of "-03 - mcpu=cortex-a57 -mfpu=neon -ffast-math" From: Ralph Campbell [mailto:ralph.campbell at broadcom.com] Sent: 09 February 2015 23:20 To: Arnaud De Grandmaison Cc: llvmdev at cs.uiuc.edu Subject: RE: aarch64 status for generating SIMD instructions So far, all I have tried is -O3 and with & without "-mcpu=cortex-a57". I'm new to LLVM so I'm not familiar with what optimization flags are available. I tried poking around in the LLVM documentation but haven't found a definitive list. The clang man page is skimpy on details. From: Arnaud A. de Grandmaison [mailto:arnaud.degrandmaison at arm.com] Sent: Monday, February 09, 2015 2:11 PM To: Ralph Campbell Cc: llvmdev at cs.uiuc.edu Subject: RE: aarch64 status for generating SIMD instructions Which compiler flags have you been using ? There is definitely support for AArch64's SIMD instructions, but their use depends on what the vectorizers can do with your code. From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Ralph Campbell Sent: 09 February 2015 22:30 To: llvmdev at cs.uiuc.edu Subject: [LLVMdev] aarch64 status for generating SIMD instructions I'm using Fedora 22 and gcc 4.9.2 to run llvm 3.5.1 on an ARM Juno reference box (cortex A53 & A57). I tried compiling some simple functions like dot product and axpy() into assembly to see if any of the SIMD instructions were generated (they weren't). Perhaps I'm missing some compiler flag to enable it. Does anyone know what the status is for aarch64 generating SIMD instructions? Anyone coordinating or leading this effort? (if there is one) -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150209/58ddafbe/attachment.html>
Michael Zolotukhin
2015-Feb-09 23:08 UTC
[LLVMdev] aarch64 status for generating SIMD instructions
Hi Ralph, A bunch of useful options for vectorizers is listed in [1]. Also, what you see might be a target-independent issue, not an aarch64-specific. If you can share the code you tested I can try to explain why vectorizer fails to handle it, and hopefully we can fix it later:) Thanks, Michael [1] http://llvm.org/docs/Vectorizers.html <http://llvm.org/docs/Vectorizers.html>> On Feb 9, 2015, at 2:19 PM, Ralph Campbell <ralph.campbell at broadcom.com> wrote: > > So far, all I have tried is –O3 and with & without “-mcpu=cortex-a57”. > I’m new to LLVM so I’m not familiar with what optimization flags are available. > I tried poking around in the LLVM documentation but haven’t found a definitive list. > The clang man page is skimpy on details. > > From: Arnaud A. de Grandmaison [mailto:arnaud.degrandmaison at arm.com] > Sent: Monday, February 09, 2015 2:11 PM > To: Ralph Campbell > Cc: llvmdev at cs.uiuc.edu > Subject: RE: aarch64 status for generating SIMD instructions > > Which compiler flags have you been using ? > > There is definitely support for AArch64’s SIMD instructions, but their use depends on what the vectorizers can do with your code. > > From: llvmdev-bounces at cs.uiuc.edu <mailto:llvmdev-bounces at cs.uiuc.edu> [mailto:llvmdev-bounces at cs.uiuc.edu <mailto:llvmdev-bounces at cs.uiuc.edu>] On Behalf Of Ralph Campbell > Sent: 09 February 2015 22:30 > To: llvmdev at cs.uiuc.edu <mailto:llvmdev at cs.uiuc.edu> > Subject: [LLVMdev] aarch64 status for generating SIMD instructions > > I’m using Fedora 22 and gcc 4.9.2 to run llvm 3.5.1 on an ARM Juno reference box (cortex A53 & A57). > I tried compiling some simple functions like dot product and axpy() into assembly to see if any of the SIMD instructions were generated (they weren’t). > Perhaps I’m missing some compiler flag to enable it. > > Does anyone know what the status is for aarch64 generating SIMD instructions? > Anyone coordinating or leading this effort? (if there is one) > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev-------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150209/ab1ff532/attachment.html>
Ralph Campbell
2015-Feb-09 23:33 UTC
[LLVMdev] aarch64 status for generating SIMD instructions
% clang -S -O3 -mcpu=cortex-a57 -ffast-math -Rpass-analysis=loop-vectorize dot.c
dot.c:15:1: remark: loop not vectorized: value that could not be identified as
reduction is used outside the loop [-Rpass-analysis=loop-vectorize]
}
^
dot.c:15:1: note: could not determine the original source location for :0:0
I found “llvm-as < /dev/null | llc -march=aarch64 -mattr=help” which listed a
bunch of features but when I tried
adding “-mfpu=neon” or “-mattr=+neon”, clang complained that the option was
unrecognized.
From: Michael Zolotukhin [mailto:mzolotukhin at apple.com]
Sent: Monday, February 09, 2015 3:08 PM
To: Ralph Campbell
Cc: Arnaud A. de Grandmaison; llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] aarch64 status for generating SIMD instructions
Hi Ralph,
A bunch of useful options for vectorizers is listed in [1].
Also, what you see might be a target-independent issue, not an aarch64-specific.
If you can share the code you tested I can try to explain why vectorizer fails
to handle it, and hopefully we can fix it later:)
Thanks,
Michael
[1] http://llvm.org/docs/Vectorizers.html
On Feb 9, 2015, at 2:19 PM, Ralph Campbell <ralph.campbell at
broadcom.com<mailto:ralph.campbell at broadcom.com>> wrote:
So far, all I have tried is –O3 and with & without “-mcpu=cortex-a57”.
I’m new to LLVM so I’m not familiar with what optimization flags are available.
I tried poking around in the LLVM documentation but haven’t found a definitive
list.
The clang man page is skimpy on details.
From: Arnaud A. de Grandmaison [mailto:arnaud.degrandmaison at arm.com]
Sent: Monday, February 09, 2015 2:11 PM
To: Ralph Campbell
Cc: llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu>
Subject: RE: aarch64 status for generating SIMD instructions
Which compiler flags have you been using ?
There is definitely support for AArch64’s SIMD instructions, but their use
depends on what the vectorizers can do with your code.
From: llvmdev-bounces at cs.uiuc.edu<mailto:llvmdev-bounces at
cs.uiuc.edu> [mailto:llvmdev-bounces at cs.uiuc.edu] On Behalf Of Ralph
Campbell
Sent: 09 February 2015 22:30
To: llvmdev at cs.uiuc.edu<mailto:llvmdev at cs.uiuc.edu>
Subject: [LLVMdev] aarch64 status for generating SIMD instructions
I’m using Fedora 22 and gcc 4.9.2 to run llvm 3.5.1 on an ARM Juno reference box
(cortex A53 & A57).
I tried compiling some simple functions like dot product and axpy() into
assembly to see if any of the SIMD instructions were generated (they weren’t).
Perhaps I’m missing some compiler flag to enable it.
Does anyone know what the status is for aarch64 generating SIMD instructions?
Anyone coordinating or leading this effort? (if there is one)
_______________________________________________
LLVM Developers mailing list
LLVMdev at cs.uiuc.edu<mailto:LLVMdev at cs.uiuc.edu>
http://llvm.cs.uiuc.edu
http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
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