Hi Duncan,
To use select, usually, there is a compare before select.
Presence of comparison will disable some opportunities to
optimize some code. Select and Compare is not associative
neither.
Thanks,
Yin
-----Original Message-----
From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On
Behalf Of Duncan Sands
Sent: Tuesday, October 30, 2012 12:38 AM
To: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Any plan to add MIN/MAX isd node?
Hi Yin,
> Do you have any plan to add MIN/MAX in ISD node?
>
> Atomic operations have Min/Max operator already. This should
>
> be easy to add Min/Max node in ISD list. Because after
>
> converting control flow into Min/Max operator, it will
>
> result in better optimization because associative attribute
>
> and can be moved around.
>
> Could you give some opinions on this issue?
what are the advantages over using "select" (or one of its codegen
variants)?
Ciao, Duncan.
_______________________________________________
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LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
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Hi Yin,> To use select, usually, there is a compare before select. > Presence of comparison will disable some opportunities to > optimize some code. Select and Compare is not associative > neither.at the IR level LLVM already has pattern matching helpers for identifying min/max idioms, here is part of a transform using this, from InstructionSimplify.cpp: // Signed variants on "max(a,b)>=a -> true". if (match(LHS, m_SMax(m_Value(A), m_Value(B))) && (A == RHS || B == RHS)) { if (A != RHS) std::swap(A, B); // smax(A, B) pred A. EqP = CmpInst::ICMP_SGE; // "A == smax(A, B)" iff "A sge B". // We analyze this as smax(A, B) pred A. P = Pred; } At the codegen level, the same could be done. Also, if a target has a max/min instruction it can transform compare+select to max/min, in fact I'm pretty sure some targets do this already. Ciao, Duncan.> > Thanks, > > Yin > > -----Original Message----- > From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu] On > Behalf Of Duncan Sands > Sent: Tuesday, October 30, 2012 12:38 AM > To: llvmdev at cs.uiuc.edu > Subject: Re: [LLVMdev] Any plan to add MIN/MAX isd node? > > Hi Yin, > >> Do you have any plan to add MIN/MAX in ISD node? >> >> Atomic operations have Min/Max operator already. This should >> >> be easy to add Min/Max node in ISD list. Because after >> >> converting control flow into Min/Max operator, it will >> >> result in better optimization because associative attribute >> >> and can be moved around. >> >> Could you give some opinions on this issue? > > what are the advantages over using "select" (or one of its codegen > variants)? > > Ciao, Duncan. > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev >
Hi Duncan,
Yes, exactly. However, we need define Opcode MIN/MAX
Into ISDOpcodes.h. Do you like to add those two definitions
Into the tree?
Thanks,
Yin
-----Original Message-----
From: Duncan Sands [mailto:duncan.sands at gmail.com] On Behalf Of Duncan Sands
Sent: Tuesday, October 30, 2012 12:10 PM
To: Yin Ma
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Any plan to add MIN/MAX isd node?
Hi Yin,
> To use select, usually, there is a compare before select.
> Presence of comparison will disable some opportunities to optimize
> some code. Select and Compare is not associative neither.
at the IR level LLVM already has pattern matching helpers for identifying
min/max idioms, here is part of a transform using this, from
InstructionSimplify.cpp:
// Signed variants on "max(a,b)>=a -> true".
if (match(LHS, m_SMax(m_Value(A), m_Value(B))) && (A == RHS || B ==
RHS))
{
if (A != RHS) std::swap(A, B); // smax(A, B) pred A.
EqP = CmpInst::ICMP_SGE; // "A == smax(A, B)" iff "A sge
B".
// We analyze this as smax(A, B) pred A.
P = Pred;
}
At the codegen level, the same could be done. Also, if a target has a
max/min instruction it can transform compare+select to max/min, in fact I'm
pretty sure some targets do this already.
Ciao, Duncan.
>
> Thanks,
>
> Yin
>
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at
cs.uiuc.edu]
> On Behalf Of Duncan Sands
> Sent: Tuesday, October 30, 2012 12:38 AM
> To: llvmdev at cs.uiuc.edu
> Subject: Re: [LLVMdev] Any plan to add MIN/MAX isd node?
>
> Hi Yin,
>
>> Do you have any plan to add MIN/MAX in ISD node?
>>
>> Atomic operations have Min/Max operator already. This should
>>
>> be easy to add Min/Max node in ISD list. Because after
>>
>> converting control flow into Min/Max operator, it will
>>
>> result in better optimization because associative attribute
>>
>> and can be moved around.
>>
>> Could you give some opinions on this issue?
>
> what are the advantages over using "select" (or one of its
codegen
> variants)?
>
> Ciao, Duncan.
>
> _______________________________________________
> LLVM Developers mailing list
> LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>