Philipp Strobel
2010-Dec-01 16:01 UTC
[LLVMdev] Problems with paged registers and seperated program and data memory
Hi
I'm hacking my own backend for a small 16 bit microprocessor. I took some
code from the msp430 backend, because there are some similarities.
But there are some features, I couldn't find a solution yet:
1. Paged Registers
The register set is a bit complicated:
it has 64 general purpose registers, and the upper 32 registers are paged
registers with 8 pages. The lower 32 registers are always page 0. So I can use
up to 256 registers. I also can use some of these paged registers as special
registers for communication with a co-processor.
There are also 16 data aliases and 16 address aliases, that can be paged too.
These aliases can page to 0..15, 16..31, 32..47 or 48..63 of the 64 general
purpose registers. These aliases are only used by load and store operations.
Right now I can use 64 registers and the aliases are hard coded, for most
apllication this is ok, but there are some applications that require more
registers. Is there support for paged registers or is there a way to describe it
in a simple way?
2. Seperated program and data memory
I have the possibility to load data from program memory and data memory, that
are seperated. I have different load operations in assembler for these two
cases. Right now, I already create code, that loads data from both but I
don't know how to check, which load operation I have to use.
Small example of a load from program memory:
C Code:
...
int values[] = {25, 13, 19, 31, 11, 99, 21, 17};
...
Assembler:
...
mov _ZZ4mainE6values, R0
add 2, R0
...
mov R0, R16
ld A0, D0 <-- this is my bad load
operation, that loads
everything
A0 is alias for R0
D0 is alias for R16
this should be "lp A0,
D0"
...
...
_ZZ4mainE6values:
.short 25 # 0x19
.short 13 # 0xd
.short 19 # 0x13
.short 31 # 0x1f
.short 11 # 0xb
.short 99 # 0x63
.short 21 # 0x15
.short 17 # 0x11
.cc_bottom _ZZ4mainE6values.data
Thanks,
Philipp
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