llvm dev - Aug 2010 - [LLVMdev] Upstream PTX backend that uses target independent code generator if possible

> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at
cs.uiuc.edu]
> On Behalf Of David A. Greene
> Sent: Tuesday, August 10, 2010 12:02 PM
> To: Che-Liang Chiou
> Cc: llvmdev at cs.uiuc.edu
> Subject: Re: [LLVMdev] Upstream PTX backend that uses target
> independent code generator if possible
> 
> Che-Liang Chiou <clchiou at gmail.com> writes:
> 
> > I surfed their code, and it seems that they didn't use code
> generator.
> > That means there design should be similar to CBackend or CPPBackend.
> > So I guess it can't generate some machine instructions like MAD,
> > and there are some PTX instruction set features that are hard to
> exploit
> > if not using code generator.
> >
> > But I didn't study their code thoroughly, so I might be wrong
about
> this.
> 
> I haven't had a chance to look at it yet either.
> 
> >>> I have tested this backend to translate a work-efficient
parallel
> scan
> >>> kernel (
> http://http.developer.nvidia.com/GPUGems3/gpugems3_ch39.html
> >>> ) into PTX code.  The generated PTX code was then executed on
real
> >>> hardware, and the result is correct.
> >>
> >> How much of the LLVM IR does this support?  What's missing?
> > Have to add some intrinsics, calling conventions, and address spaces.
> > I would say these are relatively small changes.
> 
> Are you generating masks at all?  If so, how are you doing that?
> Similarly to how the ARM backend does predicates (handling all the
> representation, etc. in the target-specific codegen)?
> 
> I've have been wanting to see predicates (vector and scalar) in the
> LLVM IR for a long time.  Perhaps the PTX backend is an opportunity
> to explore that.
[Villmow, Micah] From looking at the llvmptxbackend, it does not fully support
vector types.
This in my perspective is one of the greatest benefits of the backend
code-generator, automatic support
for vector types in LLVM-IR that are not natively supported by the target
machine via vector splitting.
> 
>                            -Dave
> 
> _______________________________________________
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> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
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My implementation of predicated instructions is similar to ARM
backend. I traced ARM and PowerPC backend for reference.

If, David, you were saying a implementation of predication in LLVM IR,
I didn't do that.  It was partly because I was not (and is still not)
very familiar with LLVM's design; so I didn't know how to do that.

I agree what Micah said; LLVM's code generator has a vector splitting,
among many other reusable components.

Regards,
Che-Liang

On Tue, Aug 10, 2010 at 12:25 PM, Villmow, Micah <Micah.Villmow at
amd.com> wrote:
>
>
>> -----Original Message-----
>> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at
cs.uiuc.edu]
>> On Behalf Of David A. Greene
>> Sent: Tuesday, August 10, 2010 12:02 PM
>> To: Che-Liang Chiou
>> Cc: llvmdev at cs.uiuc.edu
>> Subject: Re: [LLVMdev] Upstream PTX backend that uses target
>> independent code generator if possible
>>
>> Che-Liang Chiou <clchiou at gmail.com> writes:
>>
>> > I surfed their code, and it seems that they didn't use code
>> generator.
>> > That means there design should be similar to CBackend or
CPPBackend.
>> > So I guess it can't generate some machine instructions like
MAD,
>> > and there are some PTX instruction set features that are hard to
>> exploit
>> > if not using code generator.
>> >
>> > But I didn't study their code thoroughly, so I might be wrong
about
>> this.
>>
>> I haven't had a chance to look at it yet either.
>>
>> >>> I have tested this backend to translate a work-efficient
parallel
>> scan
>> >>> kernel (
>> http://http.developer.nvidia.com/GPUGems3/gpugems3_ch39.html
>> >>> ) into PTX code.  The generated PTX code was then executed
on real
>> >>> hardware, and the result is correct.
>> >>
>> >> How much of the LLVM IR does this support?  What's
missing?
>> > Have to add some intrinsics, calling conventions, and address
spaces.
>> > I would say these are relatively small changes.
>>
>> Are you generating masks at all?  If so, how are you doing that?
>> Similarly to how the ARM backend does predicates (handling all the
>> representation, etc. in the target-specific codegen)?
>>
>> I've have been wanting to see predicates (vector and scalar) in the
>> LLVM IR for a long time.  Perhaps the PTX backend is an opportunity
>> to explore that.
> [Villmow, Micah] From looking at the llvmptxbackend, it does not fully
support vector types.
> This in my perspective is one of the greatest benefits of the backend
code-generator, automatic support
> for vector types in LLVM-IR that are not natively supported by the target
machine via vector splitting.
>>
>>                            -Dave
>>
>> _______________________________________________
>> LLVM Developers mailing list
>> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>

"Villmow, Micah" <Micah.Villmow at amd.com> writes:
>> I've have been wanting to see predicates (vector and scalar) in the
>> LLVM IR for a long time.  Perhaps the PTX backend is an opportunity
>> to explore that.
> [Villmow, Micah] From looking at the llvmptxbackend, it does not fully
> support vector types.  This in my perspective is one of the greatest
> benefits of the backend code-generator, automatic support for vector
> types in LLVM-IR that are not natively supported by the target machine
> via vector splitting.
Actually, one doesn't really need vector types for PTX at the codegen
level unless one wants to make use of the 128-bit memory loads and
stores.  This is because the programming model at the asm level is
almost entirely scalar.  But we do certainly want masking capability on
scalar instructions.  If the backend doesn't have that it's going to
generate horribly performing code.

                              -Dave

Che-Liang Chiou <clchiou at gmail.com> writes:
> My implementation of predicated instructions is similar to ARM
> backend. I traced ARM and PowerPC backend for reference.
Cool.
> If, David, you were saying a implementation of predication in LLVM IR,
> I didn't do that.  It was partly because I was not (and is still not)
> very familiar with LLVM's design; so I didn't know how to do that.
No, I wouldn't have expected you to do that, but I think long-term we
will want to consider it.

                               -Dave