I'm working on adding some more annotations to asm and I cam across this odd construct generated for X86/split-vector-rem.ll: movss %xmm0, 32(%rsp) # Scalar Spill [...] unpcklps 48(%rsp), %xmm0 # Vector Folded Reload [...] movaps %xmm0, 16(%rsp) # Vector Spill [...] unpcklps 32(%rsp), %xmm0 # Vector Folded Reload How is this possibly legal? First we spill %xmm0 (a 32-bit value) to a stack slot that's onlt 16 bits wide (the next $rsp offsets are 48 and 16). Then we load 64 bits from 32(%rsp) via unpcklps and consider it a reload of the spill. This seems really wrong. Can someone explain? -Dave
On Friday 20 November 2009 14:49, David Greene wrote:> I'm working on adding some more annotations to asm and I > cam across this odd construct generated for X86/split-vector-rem.ll: > > movss %xmm0, 32(%rsp) # Scalar Spill > [...] > unpcklps 48(%rsp), %xmm0 # Vector Folded > Reload [...] > movaps %xmm0, 16(%rsp) # Vector Spill > [...] > unpcklps 32(%rsp), %xmm0 # Vector Folded > Reload > > How is this possibly legal? First we spill %xmm0 (a 32-bit value) > to a stack slot that's onlt 16 bits wide (the next $rsp offsets are 48 > and 16). Then we load 64 bits from 32(%rsp) via unpcklps and consider it a > reload of the spill. > > This seems really wrong. Can someone explain?Hah. I am silly. bytes != bits. I've been working in LLVM codegen for too long. :) -Dave
Seemingly Similar Threads
- [LLVMdev] Unexpected spilling of vector register during lane extraction on some x86_64 targets
- [LLVMdev] x86-64 backend generates aligned ADDPS with unaligned address
- [LLVMdev] x86-64 backend generates aligned ADDPS with unaligned address
- RFC: A proposal for vectorizing loops with calls to math functions using SVML
- RFC: A proposal for vectorizing loops with calls to math functions using SVML