Evan,> It's trying to find the register class for register #79 and VT #4. You > can look up 79 from X86GenRegisterNames.inc (it's RDX), VT #4 is > MVT::i32. So scheduler blows up. This is probably a upstream lowering > bug.Yes. Exactly. I've described in bugzilla a reason. Could you please comment? -- With best regards, Anton Korobeynikov. Faculty of Mathematics & Mechanics, Saint Petersburg State University.
Maybe Matching Threads
- [LLVMdev] Exception Problems
- [LLVMdev] bitconvert for multi-typed RegisterClasses
- [LLVMdev] Assert in SelectionDAGLegalize when using arbitrary size integers
- [LLVMdev] [PATCH] Add new phase to legalization to handle vector operations
- 64 bit mask in x86vshuffle instruction