llvm dev - Jul 2004 - [LLVMdev] Callee saved register, almost

I've another problem. There's one register, gr6, which is used to return
high
part of return value for functions returning 64-bit values. For such 
functions, the register should not be saved, naturally.

But when function does not return 64-bit value, then the register must be 
saved. How can I express this in .td file?

- Volodya

Vladimir Prus wrote:
> I've another problem. There's one register, gr6, which is used to
return
> high part of return value for functions returning 64-bit values. For such
> functions, the register should not be saved, naturally.
>
> But when function does not return 64-bit value, then the register must be
> saved. How can I express this in .td file?
Ok, I've managed to do what I what by not marking the register as callee 
saved, and saving it manually in prologue/epilogue generation code.

- Volodya

On Thu, 8 Jul 2004, Vladimir Prus wrote:
> Vladimir Prus wrote:
> > I've another problem. There's one register, gr6, which is used
to return
> > high part of return value for functions returning 64-bit values. For
such
> > functions, the register should not be saved, naturally.
> >
> > But when function does not return 64-bit value, then the register must
be
> > saved. How can I express this in .td file?
>
> Ok, I've managed to do what I what by not marking the register as
callee
> saved, and saving it manually in prologue/epilogue generation code.
That will definitely work, but it will lead to slightly inefficient code
in some cases.  I think that the proper fix for this is to make the
MRegisterInfo::getCalleeSaveRegs() method take a pointer to the
MachineFunction being code generated.  It could then return different sets
based on arbitrary properties that the target is interested in.

To use this, the tablegen description would have to be extended a bit to
support defining the Target::CalleeSavedRegisters property as a code
block (similar to how the allocation_order code works in the
RegisterClass class).

-Chris

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